Semiconductor device and method of manufacturing the same

ABSTRACT

After a sputtering gas is supplied to a deposition chamber, plasma including an ion of the sputtering gas is generated in the vicinity of a target. The ion of the sputtering gas is accelerated and collides with the target, so that flat-plate particles and atoms of the target are separated from the target. The flat-plate particles are deposited with a gap therebetween so that the flat plane faces a substrate. The atom and the aggregate of the atoms separated from the target enter the gap between the deposited flat-plate particles and grow in the plane direction of the substrate to fill the gap. A film is formed over the substrate. After the deposition, heat treatment is performed at high temperature in an oxygen atmosphere, which forms an oxide with a few oxygen vacancies and high crystallinity.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.14/953,632, filed Nov. 30, 2015, now allowed, which claims the benefitof foreign priority applications filed in Japan as Serial No.2014-242856 on Dec. 1, 2014, Serial No. 2015-047546 on Mar. 10, 2015,Serial No. 2015-118401 on Jun. 11, 2015, and Serial No. 2015-126832 onJun. 24, 2015, all of which are incorporated by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

One embodiment of the present invention relates to a semiconductordevice including an oxide semiconductor, a method of manufacturing anoxide, or a method of testing an oxide.

Note that one embodiment of the present invention is not limited to theabove technical field. The technical field of the invention disclosed inthis specification and the like relates to an object, a method, or amanufacturing method. In addition, one embodiment of the presentinvention relates to a process, a machine, manufacture, or a compositionof matter. Specifically, examples of the technical field of oneembodiment of the present invention disclosed in this specificationinclude a semiconductor device, a display device, a liquid crystaldisplay device, a light-emitting device, a power storage device, animaging device, a memory device, a processor, an electronic device, amethod for driving any of them, a method for manufacturing any of them,and a method for testing any of them.

2. Description of the Related Art

In recent years, display devices have been used in various electronicdevices such as television receivers, personal computer monitors, andsmart phones, and the performance of the display devices has beenimproved to achieve higher definition, lower power consumption, andother various objectives.

In addition, semiconductor devices such as central processing units(CPUs), memories, and sensors have been used in various electronicdevices such as personal computers, smart phones, and digital cameras.The performance of the semiconductor devices has also been improved toachieve miniaturization, lower power consumption, and other variousobjectives.

One of the ways that have been proposed to achieve higher performancesuch as higher definition, lower power consumption, and miniaturizationis the use of an oxide semiconductor for a semiconductor layer(hereinafter also referred to as an active layer, a channel layer, or achannel formation region) of a transistor in a semiconductor device. Anexample of the transistor includes an oxide of indium, gallium, and zinc(hereinafter also referred to as an In—Ga—Zn oxide) for a channel layer(see Patent Document 4).

In particular, a transistor using an oxide semiconductor in a channellayer is used as a switching element or the like in a display device(Patent Documents 1 and 2).

Oxide semiconductors have been researched since early times. In 1988,there was a disclosure of a crystal In—Ga—Zn oxide that can be used fora semiconductor element (see Patent Document 3).

In 2013, it is reported that an amorphous In—Ga—Zn oxide whosecrystallization is promoted by irradiation with an electron beam has anunstable structure and that the formed amorphous In—Ga—Zn oxide has noordering in observation with a high-resolution transmission electronmicroscope (see Non-Patent Document 1).

In 2014, electric characteristics and reliability of a transistor usingan amorphous In—Sn—Zn oxide were reported (see Non-Patent Document 6).It was reported that, in the transistor using an amorphous In—Sn—Znoxide, electrons accelerated by an electric field generated inside theoxide form a plurality of carriers because of impact ionization, whichleads to deterioration with an increase in drain current.

In 2014, it was also reported that a transistor including a crystallineIn—Ga—Zn oxide has more excellent electrical characteristics and higherreliability than a transistor including an amorphous In—Ga—Zn oxide (seeNon-Patent Documents 2 to 4). These documents report that a crystalboundary is not clearly observed in an In—Ga—Zn oxide including a c-axisaligned a-b-plane-anchored crystalline oxide semiconductor (CAAC-OS).

As a kind of a structure of polymer crystal, a concept of “paracrystal”is known. A paracrystal seemingly has a trace of crystal lattice;however, compared with an ideal single crystal, the paracrystal has adistorted crystal structure (see Non-Patent Document 5).

REFERENCES Patent Documents

-   Patent Document 1: Japanese Published Patent Application No.    2007-123861-   Patent Document 2: Japanese Published Patent Application No.    2007-96055-   Patent Document 3: Japanese Published Patent Application No.    S63-239117-   Patent Document 4: Japanese Translation of PCT International    Application No. H11-505377-   Patent Document 5: Japanese Published Patent Application No.    H6-275697

Non-Patent Documents

-   Non-Patent Document 1: T. Kamiya, Koji Kimoto, N. Ohashi, K. Abe, Y.    Hanyu, H. Kumomi, and H. Hosono, “Electron-Beam-Induced    Crystallization of Amorphous In—Ga—Zn—O Thin Films Fabricated by UHV    Sputtering”, Proceedings of The 20th International Display    Workshops, 2013, AMD2-5L-   Non-Patent Document 2: S. Yamazaki, H. Suzawa, K. Inoue, K. Kato, T.    Hirohashi, K. Okazaki, and N. Kimizuka, “Properties of crystalline    In—Ga—Zn-oxide semiconductor and its transistor characteristics”,    Japanese Journal of Applied Physics, vol. 53, 2014, 04ED18-   Non-Patent Document 3: S. Yamazaki, T. Hirohashi, M. Takahashi, S.    Adachi, M. Tsubuku, J. Koezuka, K. Okazaki, Y. Kanzaki, H.    Matsukizono, S. Kaneko, S. Mori, and T. Matsuo, “Back-channel-etched    thin-film transistor Using c-axis-aligned crystal In—Ga—Zn Oxide”,    Journal of the Society for Information Display, 8 Apr. 2014, Volume    22, Issue 1, pp. 55-67-   Non-Patent Document 4: S. Yamazaki, “Crystalline Oxide Semiconductor    Using CAAC-IGZO and its Application,” The Electrochemical Society    Transactions, 2014, vol. 64(10), pp. 155-164-   Non-Patent Document 5: Rolf Hosemann, “Crystalline and    Paracrystalline Order in High Polymers”, Journal of Applied Physics,    January 1963, vol. 34, number. 1, pp. 25-41-   Non-Patent Document 6: Y. Uraoka, S. Urakawa, Y. Ishikawa: “Analysis    of Thermal Degradation in Oxide Thin Film Transistor”, The    Electrochemical Society Transactions, 2014, vol. 64(10), pp. 71-78.

SUMMARY OF THE INVENTION

Semiconductor devices used as components of electronic devices need tobe resistant to heat, electricity, light, or the like in accordance withuses and use environments of the electronic devices. For example, heatgenerated inside an electronic device during operation might cause asemiconductor device to break down. Alternatively, ultraviolet raysemitted on a semiconductor device, the ambient temperature of anelectronic device, or the like might cause a breakdown when theelectronic device is used outdoors.

As described above, a breakdown of an electronic device can be due to anincident in a semiconductor device itself, such as heat generation inthe electronic device, or due to an external environment such asultraviolet rays and the ambient temperature.

A semiconductor which is one of components of a transistor used in asemiconductor device is affected by, for example, heat, light, orcurrent flowing through the semiconductor device. If affectedsignificantly, the semiconductor deteriorates, which might degradecurrent characteristics of the transistor including the semiconductor.Specific deterioration examples of the transistor are a shift inthreshold voltage and occurrence of short-channel effects.

The following tests measure characteristics and reliability of atransistor in a use environment: a bias-temperature stress test(hereinafter, also referred to as a BT test); and a test for observingor measuring current characteristics, temperature, light emission, orthe like with respect to the time during which a high potential is keptbeing applied between two electrodes, a gate electrode and a source ordrain electrode of a transistor.

In the above tests for a transistor, the behavior and lifetime of thetransistor is examined in such a manner that a large load such as a highpotential or heat is applied to the transistor to advance deteriorationof a semiconductor. The application of a high potential betweenelectrodes of the transistor might cause conduction with anotherelectrode because of a foreign substance (e.g., dust or a residue), aremaining component (e.g., water or hydrogen), a structural defect, orthe like in the semiconductor, which might result in a problem such asunintended current flow between electrodes.

In particular, in a transistor including an oxide semiconductor, adefect due to oxygen vacancies in the oxide semiconductor might causecurrent to flow between electrodes of the transistor.

An object of one embodiment of the present invention is to provide amethod of manufacturing an oxide that can be used as a semiconductor ofa transistor or the like. An object is to provide a method ofmanufacturing, for example, an oxide with fewer defects such as grainboundaries or oxygen vacancies.

Another object of one embodiment of the present invention is to providea novel semiconductor device or the like using an oxide as asemiconductor. Another object of one embodiment of the present inventionis to provide a module that includes a semiconductor device using anoxide as a semiconductor. Another object of one embodiment of thepresent invention is to provide an electronic device using a module thatincludes a semiconductor device using an oxide as a semiconductor.Another object of one embodiment of the present invention is to providea novel semiconductor device, a novel display device, a novel module, anovel electronic device, or the like.

Another object of one embodiment of the present invention is to providea transistor that is resistant to heat generated from itself and asemiconductor device using the transistor. Another object of oneembodiment of the present invention is to provide a transistor that isunlikely to depend on the ambient temperature and a semiconductor deviceusing the transistor. Another object of one embodiment of the presentinvention is to provide a transistor that can withstand high current andhigh voltage and a semiconductor device using the transistor. Anotherobject of one embodiment of the present invention is to provide atransistor having favorable electrical characteristics and asemiconductor device using the transistor. Another object of oneembodiment of the present invention is to provide a transistor havingstable electrical characteristics and a semiconductor device using thetransistor. Another object of one embodiment of the present invention isto provide a transistor having low off-state current and a semiconductordevice using the transistor.

Another object of one embodiment of the present invention is to providea method of testing oxygen vacancies in the oxide semiconductor used inthe transistor. Another object of one embodiment of the presentinvention is to provide a method of quantitatively testing the amount ofoxygen in an oxide semiconductor, an insulator, and a conductor that areincluded in the transistor.

Note that the objects of one embodiment of the present invention are notlimited to the above objects. The objects described above do not disturbthe existence of other objects. The other objects are ones that are notdescribed above and will be described below. The other objects will beapparent from and can be derived from the description of thespecification, the drawings, and the like by those skilled in the art.One embodiment of the present invention solves at least one of the aboveobjects and/or the other objects. One embodiment of the presentinvention need not solve all the aforementioned objects and/or the otherobjects.

(1)

One embodiment of the present invention is a semiconductor deviceincluding a transistor. The transistor includes an oxide that includesindium, zinc, and an element M (M is any one of aluminum, gallium,yttrium, and tin) and has a c-axis-aligned crystalline structure. Thecarrier density of the oxide is less than 8×10¹¹/cm³, and the filmdensity of the oxide is greater than or equal to 90% of a film densityobtained when the oxide has a single crystal structure. The transistorhas a property of withstanding voltage and a property of withstandingcurrent.

(2)

Another embodiment of the present invention is the semiconductor deviceaccording to (1), in which the carrier density of the oxide is less than1×10¹¹/cm³ and greater than or equal to 1×10⁻⁹/cm³.

(3)

Another embodiment of the present invention is the semiconductor deviceaccording to (1) or (2), in which the spin density of a signal observedby electron spin resonance (ESR) of the oxide at a g-factor greater thanor equal to 1.90 and less than or equal to 1.95 is less than or equal to1×10¹⁷ spins/cm³.

(4)

Another embodiment of the present invention is the semiconductor deviceaccording to any one of (1) to (3), in which the transistor includesfirst to third conductive films, an insulating film, and first to thirdoxide semiconductor films. The second oxide semiconductor film comprisesthe oxide. The second oxide semiconductor film comprises a first regionbetween the first oxide semiconductor film and the third oxidesemiconductor film. The first conductive film comprises a second regionin contact with at least any of the first to third oxide semiconductorfilms. The second conductive film comprises a third region in contactwith at least any of the first to third oxide semiconductor films. Theinsulating film comprises a fourth region in contact with a top surfaceof the third oxide semiconductor film. The third conductive film and thefirst region overlap with each other with the insulating film interposedtherebetween.

(5)

Another embodiment of the present invention is the semiconductor deviceaccording to any one of (1) to (3), in which the transistor includesfirst to third conductive films, an insulating film, and first to thirdoxide semiconductor films. The second oxide semiconductor film comprisesthe oxide. The second oxide semiconductor film comprises a first regionlocated between the first oxide semiconductor film and the third oxidesemiconductor film. The first conductive film comprises a second regionin contact with at least any of the first to third oxide semiconductorfilms. The second conductive film comprises a third region in contactwith at least any of the first to third oxide semiconductor films. Theinsulating film comprises a fourth region in contact with a lowerportion of the first oxide semiconductor film. The third conductive filmand the first region overlap with each other with the insulating filminterposed therebetween.

(6)

Another embodiment of the present invention is the semiconductor deviceaccording to (4) or (5), wherein at least one of the first and thirdoxide semiconductor films comprises the oxide.

(7)

Another embodiment of the present invention is a method of manufacturingan oxide by a sputtering method using a deposition chamber, a target inthe deposition chamber, and a substrate, the oxide having ac-axis-aligned crystalline structure, a carrier density less than8×10¹¹/cm³, and a film density greater than or equal to 90% of a filmdensity obtained when the oxide has a single crystal structure. Themethod includes the following steps: after supplying a sputtering gascontaining oxygen and/or a rare gas into the deposition chamber,generating a potential difference between the target and the substrate,thereby generating plasma including an ion of the sputtering gas in thevicinity of the target; accelerating the ion of the sputtering gastoward the target by the potential difference; separating a plurality offlat-plate particles of a compound containing a plurality of elements,an atom of the target, and an aggregate of atoms of the target from thetarget by collision of the accelerated ion of the sputtering gas withthe target; negatively charging surfaces of the plurality of flat-plateparticles that receive a negative charge from an ion of the sputteringgas while the plurality of flat-plate particles fly in the plasma;depositing one of the negatively charged flat-plate particles so thatthe surface faces the substrate; depositing another negatively chargedflat-plate particle in a region apart from the one negatively chargedflat-plate particle over the substrate while the one negatively chargedflat-plate particle and the another negatively charged flat-plateparticle repel each other; placing the atom and the aggregate of theatoms into a gap between the one negatively charged flat-plate particleand the another negatively charged flat-plate particle; and growing theatom and the aggregate of the atoms in a lateral direction in the gapbetween the flat-plate particles, so that the gap between the onenegatively charged flat-plate particle and the another negativelycharged flat-plate particle is filled with the atom and the aggregate ofthe atoms.

(8)

Another embodiment of the present invention is the method ofmanufacturing an oxide according to (7), in which the atom and theaggregate are grown in the lateral direction from the flat-plateparticle so as to have the same structure as the flat-plate particle,and the gap between the flat-plate particles is filled.

(9)

Another embodiment of the present invention is the method ofmanufacturing an oxide according to (7) or (8), in which the flat-plateparticles are stacked to form a thin film structure.

(10)

Another embodiment of the present invention is the method ofmanufacturing an oxide according to any one of (7) to (9), in whichafter formation of the oxide, thermal annealing or rapid thermalannealing (RTA) is performed at a temperature that is higher than atemperature at which the oxide is formed and that is lower than atemperature at which the oxide comes to have a different crystalstructure, so that the oxide is made to have a high density or to be asingle crystal.

(11)

Another embodiment of the present invention is the method ofmanufacturing an oxide according to (10), in which the temperature ofthe thermal annealing or RTA is higher than 300° C. and lower than 1500°C.

(12)

Another embodiment of the present invention is the method ofmanufacturing an oxide according to (11), wherein the thermal annealingor the RTA is performed in an oxygen atmosphere.

(13)

Another embodiment of the present invention is the method ofmanufacturing an oxide according to any one of (7) to (12), in which theoxide is formed on a surface having an amorphous structure.

(14)

Another embodiment of the present invention is the method of forming anoxide according to any one of (7) to (13), in which the target includesindium, zinc, an element M (M is any one of aluminum, gallium, yttrium,and tin), and oxygen, and the target has a region with a polycrystallinestructure.

(15)

Another embodiment of the present invention is a semiconductor devicecomprising a transistor, the transistor comprising the oxide accordingto any one of (7) to/or (14)

According to one embodiment of the present invention, a method offorming an oxide that can be used as a semiconductor of a transistor orthe like can be provided. In particular, a method of forming an oxidewith fewer defects such as grain boundaries or oxygen vacancies can beprovided.

According to one embodiment of the present invention, a novelsemiconductor device using an oxide as a semiconductor can be provided.According to one embodiment of the present invention, a module thatincludes a semiconductor device using an oxide as a semiconductor can beprovided. According to one embodiment of the present invention, anelectronic device including a module that includes a semiconductordevice using an oxide as a semiconductor can be provided. According toone embodiment of the present invention, a novel semiconductor device, anovel display device, a novel module, a novel electronic device or thelike can be provided.

According to another embodiment of the present invention, a transistorthat is resistant to heat generated from itself and a semiconductordevice using the transistor can be provided. According to anotherembodiment of the present invention, a transistor that is unlikely todepend on the ambient temperature and a semiconductor device using thetransistor can be provided. According to another embodiment of thepresent invention, a transistor that can withstand high current and highvoltage and a semiconductor device using the transistor can be provided.According to another embodiment of the present invention, a transistorhaving favorable electrical characteristics and a semiconductor deviceusing the transistor can be provided. According to another embodiment ofthe present invention, a transistor having stable electricalcharacteristics and a semiconductor device using the transistor can beprovided. Another object of one embodiment of the present invention isto provide a transistor having low off-state current and a semiconductordevice using the transistor can be provided.

According to another embodiment of the present invention, a method oftesting oxygen vacancies in the oxide semiconductor used in thetransistor can be provided. According to another embodiment of thepresent invention, a method of quantitatively testing the amount ofoxygen in an oxide semiconductor, an insulator, and a conductor that areincluded in the transistor can be provided.

Note that the effects of one embodiment of the present invention are notlimited to the above effects. The effects described above do not disturbthe existence of other effects. The other effects are ones that are notdescribed above and will be described below. The other effects will beapparent from and can be derived from the description of thespecification, the drawings, and the like by those skilled in the art.One embodiment of the present invention has at least one of the aboveeffects and/or the other effects. Accordingly, one embodiment of thepresent invention does not have the aforementioned effects in somecases.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A to 1D are Cs-corrected high-resolution TEM images of a crosssection of a CAAC-OS and a cross-sectional schematic view of theCAAC-OS;

FIGS. 2A to 2D are Cs-corrected high-resolution TEM images of a plane ofa CAAC-OS;

FIGS. 3A to 3C show structural analysis of a CAAC-OS and a singlecrystal oxide semiconductor by XRD;

FIGS. 4A and 4B show electron diffraction patterns of a CAAC-OS;

FIG. 5 shows a change in crystal parts of In—Ga—Zn oxide by electronirradiation;

FIGS. 6A to 6D illustrate an example of a deposition method of aCAAC-OS;

FIG. 7 illustrates an InMZnO4 crystal;

FIGS. 8A to 8E illustrate an example of a deposition method of aCAAC-OS;

FIGS. 9A to 9C illustrate an example of a deposition method of aCAAC-OS;

FIG. 10 illustrates an example of a deposition method of an nc-OS;

FIG. 11 is a ternary diagram showing the composition of an In-M-Znoxide;

FIGS. 12A and 12B are a top view and a cross-sectional view illustratinga structural example of a transistor;

FIGS. 13A and 13B are cross-sectional views each illustrating astructural example of a transistor;

FIGS. 14A and 14B are a top view and a cross-sectional view illustratinga structural example of a transistor;

FIGS. 15A and 15B are a top view and a cross-sectional view illustratinga structural example of a transistor;

FIGS. 16A and 16B are a top view and a cross-sectional view illustratinga structural example of a transistor;

FIGS. 17A and 17B are a top view and a cross-sectional view illustratinga structural example of a transistor;

FIGS. 18A and 18B are cross-sectional views each illustrating astructural example of a transistor;

FIG. 19 shows calculation conditions of a transistor;

FIG. 20 shows film densities of oxide semiconductors;

FIGS. 21A to 21C show ESR measurement results of oxide semiconductors;

FIG. 22 shows spin densities of the oxide semiconductors;

FIG. 23 is a block diagram illustrating an example of a CPU;

FIG. 24 is a circuit diagram showing an example of a semiconductordevice;

FIG. 25 is a circuit diagram showing an example of a semiconductordevice;

FIGS. 26A and 26B illustrate structural examples of a chip and a module;

FIG. 27 is a block diagram showing a structural example of an RFIC;

FIG. 28 is a block diagram showing an example of a memory device;

FIG. 29 is a circuit diagram showing an example of a memory cell;

FIG. 30 is a circuit diagram showing an example of a memory cell;

FIG. 31 is a circuit diagram showing an example of a memory cell;

FIGS. 32A to 32F illustrate examples of electronic devices;

FIGS. 33A and 33B are a top view and a cross-sectional view illustratinga structural example of an imaging device;

FIG. 34 is a circuit diagram showing an example of the imaging device;

FIG. 35 shows calculation conditions of a transistor;

FIGS. 36A and 36B show calculation results of a transistor;

FIGS. 37A and 37B show calculation results of the transistor;

FIG. 38 shows calculation results of the transistor;

FIG. 39 illustrates a structural example of a transistor;

FIG. 40 shows structural analysis of In—Sn—Zn oxide semiconductors byXRD;

FIGS. 41A to 41C show cross-sectional TEM images of the In—Sn—Zn oxidesemiconductors;

FIGS. 42A to 42C show an electron diffraction pattern of an In—Sn—Znoxide semiconductor;

FIG. 43 shows results of bias-temperature stress tests of transistors;

FIG. 44 shows results of a bias-temperature stress test of a transistor;

FIGS. 45A and 45B show CPM measurement results of In—Sn—Zn oxidesemiconductors;

FIG. 46 shows CPM measurement results of the In—Sn—Zn oxidesemiconductors;

FIG. 47 shows results of bias-temperature stress tests of transistors;

FIGS. 48A and 48B show images of transistors taken with an emissionmicroscope;

FIGS. 49A and 49B show an image of a transistor taken with an opticalmicroscope and cross-sectional views and current images of thetransistor;

FIGS. 50A and 50B show an image of a transistor taken with an opticalmicroscope and cross-sectional views and current images of thetransistor;

FIGS. 51A and 51B show an image of a transistor taken with an opticalmicroscope and cross-sectional views and current images of thetransistor;

FIGS. 52A to 52C illustrate calculation conditions of a transistor;

FIG. 53 shows calculation results of the transistor;

FIGS. 54A to 54C show results of bias-temperature stress tests oftransistors;

FIG. 55 shows images of transistors taken with an emission microscope;

FIGS. 56A and 56B show results of bias-temperature stress tests oftransistors;

FIGS. 57A and 57B show results of bias-temperature stress tests oftransistors; and

FIG. 58 illustrates a structural example of a transistor.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiment of the present invention will be described indetail with the reference to the drawings. However, the presentinvention is not limited to the description below, and it is easilyunderstood by those skilled in the art that modes and details disclosedherein can be modified in various ways. Furthermore, the presentinvention is not construed as being limited to description of theembodiments and the examples. In describing structures of the presentinvention with reference to the drawings, common reference numerals areused for the same portions in different drawings. Note that the samehatched pattern is applied to similar parts, and the similar parts arenot especially denoted by reference numerals in some cases.

Note that the size, the thickness of films (layers), or regions indrawings is sometimes exaggerated for simplicity.

A voltage usually refers to a potential difference between a givenpotential and a reference potential (e.g., a source potential or aground potential (GND)). A voltage can be referred to as a potential andvice versa.

In this specification and the like, ordinal numbers such as “first”,“second”, and “third” are used in order to avoid confusion amongcomponents. Thus, the terms do not limit the number or order ofcomponents. For example, in the present specification and the like, a“first” component in one embodiment can be referred to as a “second”component in other embodiments or claims. Furthermore, in the presentspecification and the like, a “first” component in one embodiment can bereferred to without the ordinal number in other embodiments or claims.

The same elements or elements having similar functions, elements formedusing the same material, elements formed at the same time, or the likein the drawings are denoted by the same reference numerals in somecases, and the description thereof is not repeated in some cases.

Note that a “semiconductor” includes characteristics of an “insulator”in some cases when the conductivity is sufficiently low, for example.Furthermore, a “semiconductor” and an “insulator” cannot be strictlydistinguished from each other in some cases because a border between the“semiconductor” and the “insulator” is not clear. Accordingly, a“semiconductor” in this specification can be called an “insulator” insome cases. Similarly, an “insulator” in this specification can becalled a “semiconductor” in some cases.

Furthermore, a “semiconductor” includes characteristics of a “conductor”in some cases when the conductivity is sufficiently high, for example.Furthermore, a “semiconductor” and a “conductor” cannot be strictlydistinguished from each other in some cases because a border between the“semiconductor” and the “insulator” is not clear. Accordingly, a“semiconductor” in this specification can be called a “conductor” insome cases. Similarly, a “conductor” in this specification can be calleda “semiconductor” in some cases.

Note that an impurity in a semiconductor refers to, for example,elements other than the main components of a semiconductor layer. Forexample, an element with a concentration lower than 0.1 atomic % is animpurity. When an impurity is contained, the density of states (DOS) maybe formed in a semiconductor, the carrier mobility may be decreased, orthe crystallinity may be decreased, for example. In the case where thesemiconductor is an oxide semiconductor, examples of an impurity whichchanges characteristics of the semiconductor include Group 1 elements,Group 2 elements, Group 14 elements, Group 15 elements, and transitionmetals other than the main components; specifically, there are hydrogen(included in water), lithium, sodium, silicon, boron, phosphorus,carbon, and nitrogen, for example. In the case of an oxidesemiconductor, oxygen vacancy may be formed by entry of impurities suchas hydrogen. Furthermore, when the semiconductor layer is silicon,examples of an impurity which changes the characteristics of thesemiconductor include oxygen, Group 1 elements except hydrogen, Group 2elements, Group 13 elements, and Group 15 elements.

In this specification, the phrase “A has a region with a concentrationB” includes, for example, “the concentration of the entire region in aregion of A in the depth direction is B”, “the average concentration ina region of A in the depth direction is B”, “the median value of aconcentration in a region of A in the depth direction is B”, “themaximum value of a concentration in a region of A in the depth directionis B”, “the minimum value of a concentration in a region of A in thedepth direction is B”, “a convergence value of a concentration in aregion of A in the depth direction is B”, and “a concentration in aregion of A in which a probable value is obtained in measurement is B”.

In this specification, the phrase “A has a region with a size B, alength B, a thickness B, a width B, or a distance B” includes, forexample, “the size, the length, the thickness, the width, or thedistance of the entire region in a region of A is B”, “the average valueof the size, the length, the thickness, the width, or the distance of aregion of A is B”, “the median value of the size, the length, thethickness, the width, or the distance of a region of A is B”, “themaximum value of the size, the length, the thickness, the width, or thedistance of a region of A is B”, “the minimum value of the size, thelength, the thickness, the width, or the distance of a region of A isB”, “a convergence value of the size, the length, the thickness, thewidth, or the distance of a region of A is B”, and “the size, thelength, the thickness, the width, or the distance of a region of A inwhich a probable value is obtained in measurement is B”.

Note that the channel length refers to, for example, a distance betweena source (a source region or a source electrode) and a drain (a drainregion or a drain electrode) in a region where a semiconductor (or aportion where a current flows in a semiconductor when a transistor ison) and a gate electrode overlap with each other or a region where achannel is formed in a top view of the transistor. In one transistor,channel lengths in all regions are not necessarily the same. In otherwords, the channel length of one transistor is not limited to one valuein some cases. Therefore, in this specification, the channel length isany one of values, the maximum value, the minimum value, or the averagevalue in a region where a channel is formed.

A channel width refers to, for example, the length of a portion where asource and a drain face each other in a region where a semiconductor (ora portion where a current flows in a semiconductor when a transistor ison) and a gate electrode overlap with each other, or a region where achannel is formed in a top view. In one transistor, channel widths inall regions do not necessarily have the same value. In other words, achannel width of one transistor is not fixed to one value in some cases.Therefore, in this specification, a channel width is any one of values,the maximum value, the minimum value, or the average value in a regionwhere a channel is formed.

Note that depending on transistor structures, a channel width in aregion where a channel is formed actually (hereinafter referred to as aneffective channel width) is different from a channel width shown in atop view of a transistor (hereinafter referred to as an apparent channelwidth) in some cases. For example, in a transistor having athree-dimensional structure, an effective channel width is greater thanan apparent channel width shown in a top view of the transistor, and itsinfluence cannot be ignored in some cases. For example, in aminiaturized transistor having a three-dimensional structure, theproportion of a channel region formed in a side surface of asemiconductor is higher in some cases. In that case, an effectivechannel width obtained when a channel is actually formed is greater thanan apparent channel width shown in the top view.

In a transistor having a three-dimensional structure, an effectivechannel width is difficult to measure in some cases. For example, toestimate an effective channel width from a design value, it is necessaryto assume that the shape of a semiconductor is known as an assumptioncondition. Therefore, in the case where the shape of a semiconductor isnot known accurately, it is difficult to measure an effective channelwidth accurately.

Therefore, in this specification, in a top view of a transistor, anapparent channel width that is a length of a portion where a source anda drain face each other in a region where a semiconductor and a gateelectrode overlap with each other is referred to as a surrounded channelwidth (SCW) in some cases. Furthermore, in this specification, in thecase where the term “channel width” is simply used, it may denote asurrounded channel width and an apparent channel width. Alternatively,in this specification, in the case where the term “channel width” issimply used, it may denote an effective channel width in some cases.Note that the values of a channel length, a channel width, an effectivechannel width, an apparent channel width, a surrounded channel width,and the like can be determined by obtaining and analyzing across-sectional TEM image and the like.

Note that in the case where electric field mobility, a current value perchannel width, and the like of a transistor are obtained by calculation,a surrounded channel width may be used for the calculation. In thatcase, a value different from one in the case where an effective channelwidth is used for the calculation is obtained in some cases.

In this specification, the term “parallel” indicates that the angleformed between two straight lines is greater than or equal to −10° andless than or equal to 10°, and accordingly also includes the case wherethe angle is greater than or equal to −5° and less than or equal to 5°.The term “substantially parallel” indicates that the angle formedbetween two straight lines is greater than or equal to −30° and lessthan or equal to 30°. The term “perpendicular” indicates that the angleformed between two straight lines is greater than or equal to 80° andless than or equal to 100°, and accordingly also includes the case wherethe angle is greater than or equal to 85° and less than or equal to 95°.The term “substantially perpendicular” indicates that the angle formedbetween two straight lines is greater than or equal to 60° and less thanor equal to 120°.

In this specification, trigonal and rhombohedral crystal systems areincluded in a hexagonal crystal system.

Embodiment 1

<Structure of Oxide Semiconductor>

First, a structure of an oxide semiconductor is described with referenceto FIGS. 1A to 1D, FIGS. 2A to 2D, FIGS. 3A to 3C, FIGS. 4A and 4B, andFIG. 5.

An oxide semiconductor is classified into a single crystal oxidesemiconductor and a non-single-crystal oxide semiconductor. Examples ofa non-single-crystal oxide semiconductor include a CAAC-OS, apolycrystalline oxide semiconductor, a nanocrystalline oxidesemiconductor (nc-OS), an amorphous-like oxide semiconductor (a-likeOS), and an amorphous oxide semiconductor.

From another perspective, an oxide semiconductor is classified into anamorphous oxide semiconductor and a crystalline oxide semiconductor.Examples of a crystalline oxide semiconductor include a single crystaloxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor,and an nc-OS.

It is known that an amorphous structure is generally defined as beingmetastable and unfixed, and being isotropic and having no non-uniformstructure. In other words, an amorphous structure has a flexible bondangle and a short-range order but does not have a long-range order.

This means that an inherently stable oxide semiconductor cannot beregarded as a completely amorphous oxide semiconductor. Moreover, anoxide semiconductor that is not isotropic (e.g., an oxide semiconductorthat has a periodic structure in a microscopic region) cannot beregarded as a completely amorphous oxide semiconductor. Note that ana-like OS has a periodic structure in a microscopic region, but at thesame time has a void and has an unstable structure. For this reason, ana-like OS has physical properties similar to those of an amorphous oxidesemiconductor.

<CAAC-OS>

First, a CAAC-OS is described.

A CAAC-OS is one of oxide semiconductors having a plurality of c-axisaligned crystal parts (also referred to as pellets).

In a combined analysis image (also referred to as a high-resolution TEMimage) of a bright-field image and a diffraction pattern of a CAAC-OS,which is obtained using a transmission electron microscope (TEM), aplurality of pellets can be observed. However, in the high-resolutionTEM image, a boundary between pellets, that is, a grain boundary is notclearly observed. Thus, in the CAAC-OS, a reduction in electron mobilitydue to the grain boundary is less likely to occur.

The CAAC-OS observed with a TEM is described below. FIG. 1A shows ahigh-resolution TEM image of a cross section of the CAAC-OS which isobserved from a direction substantially parallel to the specimensurface. The high-resolution TEM image is obtained with a sphericalaberration corrector function. The high-resolution TEM image obtainedwith a spherical aberration corrector function is particularly referredto as a Cs-corrected high-resolution TEM image. The Cs-correctedhigh-resolution TEM image can be obtained with, for example, an atomicresolution analytical electron microscope JEM-ARM200F manufactured byJEOL Ltd.

FIG. 1B is an enlarged Cs-corrected high-resolution TEM image of aregion (1) in FIG. 1A. FIG. 1B shows that metal atoms are arranged in alayered manner in a pellet. Each metal atom layer has a configurationreflecting unevenness of a surface over which the CAAC-OS is formed(hereinafter, the surface is referred to as a formation surface) or atop surface of the CAAC-OS, and is arranged parallel to the formationsurface or the top surface of the CAAC-OS.

As shown in FIG. 1B, the CAAC-OS has a characteristic atomicarrangement. The characteristic atomic arrangement is denoted by anauxiliary line in FIG. 1C. FIGS. 1B and 1C prove that the size of apellet is approximately 1 nm to 3 nm, and the size of a space caused bytilt of the pellets is approximately 0.8 nm. Therefore, the pellet canalso be referred to as a nanocrystal (nc). Furthermore, the CAAC-OS canalso be referred to as an oxide semiconductor including c-axis alignednanocrystals (CANC).

Here, according to the Cs-corrected high-resolution TEM images, theschematic arrangement of pellets 5100 of a CAAC-OS over a substrate 5120is illustrated by such a structure in which bricks or blocks are stacked(see FIG. 1D). The part in which the pellets are tilted as observed inFIG. 1C corresponds to a region 5161 shown in FIG. 1D.

FIG. 2A shows a Cs-corrected high-resolution TEM image of a plane of theCAAC-OS observed from a direction substantially perpendicular to thespecimen surface. FIGS. 2B, 2C, and 2D are enlarged Cs-correctedhigh-resolution TEM images of regions (1), (2), and (3) in FIG. 2A,respectively. FIGS. 2B, 2C, and 2D indicate that metal atoms arearranged in a triangular, quadrangular, or hexagonal configuration in apellet. However, there is no regularity of arrangement of metal atomsbetween different pellets.

Next, a CAAC-OS analyzed by X-ray diffraction (XRD) is described. Forexample, when the structure of a CAAC-OS including an InGaZnO₄ crystalis analyzed by an out-of-plane method, a peak appears at a diffractionangle (2θ) of around 31° as shown in FIG. 3A. This peak is derived fromthe (009) plane of the InGaZnO₄ crystal, which indicates that crystalsin the CAAC-OS have c-axis alignment, and that the c-axes are aligned ina direction substantially perpendicular to the formation surface or thetop surface of the CAAC-OS.

Note that in structural analysis of the CAAC-OS by an out-of-planemethod, another peak may appear when 2θ is around 36°, in addition tothe peak at 2θ of around 31°. The peak of 2θ at around 36° indicatesthat a crystal having no c-axis alignment is included in part of theCAAC-OS. It is preferable that in the CAAC-OS analyzed by anout-of-plane method, a peak appear when 2θ is around 31° and that a peaknot appear when 2θ is around 36°.

On the other hand, in structural analysis of the CAAC-OS by an in-planemethod in which an X-ray is incident on a specimen in a directionsubstantially perpendicular to the c-axis, a peak appears when 2θ isaround 56°. This peak is derived from the (110) plane of the InGaZnO₄crystal. In the case of the CAAC-OS, when analysis (ϕ scan) is performedwith 2θ fixed at around 56° and with the specimen rotated using a normalvector of the specimen surface as an axis (ϕ axis), as shown in FIG. 3B,a peak is not clearly observed. In contrast, in the case of a singlecrystal oxide semiconductor of InGaZnO₄, when ϕ scan is performed with2θ fixed at around 56°, as shown in FIG. 3C, six peaks which are derivedfrom crystal planes equivalent to the (110) plane are observed.Accordingly, the structural analysis using XRD shows that the directionsof a-axes and b-axes are irregularly oriented in the CAAC-OS.

Next, a CAAC-OS analyzed by electron diffraction is described. Forexample, when an electron beam with a probe diameter of 300 nm isincident on a CAAC-OS including an InGaZnO₄ crystal in a directionparallel to the specimen surface, a diffraction pattern (also referredto as a selected-area transmission electron diffraction pattern) shownin FIG. 4A can be obtained. In this diffraction pattern, spots derivedfrom the (009) plane of an InGaZnO₄ crystal are included. Thus, theelectron diffraction also indicates that pellets included in the CAAC-OShave c-axis alignment and that the c-axes are aligned in a directionsubstantially perpendicular to the formation surface or the top surfaceof the CAAC-OS. Meanwhile, FIG. 4B shows a diffraction pattern obtainedin such a manner that an electron beam with a probe diameter of 300 nmis incident on the same specimen in a direction perpendicular to thespecimen surface. As shown in FIG. 4B, a ring-like diffraction patternis observed. Thus, the electron diffraction also indicates that thea-axes and b-axes of the pellets included in the CAAC-OS do not haveregular alignment. The first ring in FIG. 4B is considered to be derivedfrom the (010) plane, the (100) plane, and the like of the InGaZnO₄crystal. The second ring in FIG. 4B is considered to be derived from the(110) plane and the like.

As described above, the CAAC-OS is an oxide semiconductor with highcrystallinity. Entry of impurities, formation of defects, or the likemight decrease the crystallinity of an oxide semiconductor. This meansthat the CAAC-OS has small amounts of impurities and defects (e.g.,oxygen vacancies).

Note that the impurity means an element other than the main componentsof the oxide semiconductor, such as hydrogen, carbon, silicon, or atransition metal element. For example, an element (specifically, siliconor the like) having higher strength of bonding to oxygen than a metalelement included in an oxide semiconductor extracts oxygen from theoxide semiconductor, which results in disorder of the atomic arrangementand reduced crystallinity of the oxide semiconductor. A heavy metal suchas iron or nickel, argon, carbon dioxide, or the like has a large atomicradius (or molecular radius), and thus disturbs the atomic arrangementof the oxide semiconductor and decreases crystallinity.

The characteristics of an oxide semiconductor having impurities ordefects might be changed by light, heat, or the like. Impuritiescontained in the oxide semiconductor might serve as carrier traps orcarrier generation sources, for example. Furthermore, oxygen vacanciesin the oxide semiconductor serve as carrier traps or serve as carriergeneration sources when hydrogen is captured therein.

The CAAC-OS having small amounts of impurities and oxygen vacancies isan oxide semiconductor with low carrier density (specifically, lowerthan 8×10¹¹/cm³, preferably lower than 1×10¹¹/cm³, further preferablylower than 1×10¹⁰/cm³, and is higher than or equal to 1×10⁻⁹/cm³). Suchan oxide semiconductor is referred to as a highly purified intrinsic orsubstantially highly purified intrinsic oxide semiconductor. A CAAC-OShas a low impurity concentration and a low density of defect states.Thus, the CAAC-OS can be referred to as an oxide semiconductor havingstable characteristics.

<nc-OS>

Next, an nc-OS is described.

An nc-OS has a region in which a crystal part is observed and a regionin which a crystal part is not clearly observed in a high-resolution TEMimage. In most cases, the size of a crystal part included in the nc-OSfilm is greater than or equal to 1 nm and less than or equal to 10 nm,or greater than or equal to 1 nm and less than or equal to 3 nm. Notethat an oxide semiconductor including a crystal part whose size isgreater than 10 nm and less than or equal to 100 nm is sometimesreferred to as a microcrystalline oxide semiconductor. In ahigh-resolution TEM image of the nc-OS, for example, a grain boundary isnot clearly observed in some cases. Note that there is a possibilitythat the origin of the nanocrystal is the same as that of a pellet in aCAAC-OS. Therefore, a crystal part of the nc-OS may be referred to as apellet in the following description.

In the nc-OS, a microscopic region (for example, a region with a sizegreater than or equal to 1 nm and less than or equal to 10 nm, inparticular, a region with a size greater than or equal to 1 nm and lessthan or equal to 3 nm) has a periodic atomic arrangement. There is noregularity of crystal orientation between different pellets in thenc-OS. Thus, the orientation of the whole film is not observed.Accordingly, the nc-OS cannot be distinguished from an a-like OS or anamorphous oxide semiconductor, depending on an analysis method. Forexample, when the nc-OS is analyzed by an out-of-plane method using anX-ray beam having a diameter larger than the size of a pellet, a peakwhich shows a crystal plane does not appear. Furthermore, a diffractionpattern like a halo pattern is observed when the nc-OS is subjected toelectron diffraction using an electron beam with a probe diameter (e.g.,50 nm or larger) that is larger than the size of a pellet. Meanwhile,spots appear in a nanobeam electron diffraction pattern of the nc-OSwhen an electron beam having a probe diameter close to or smaller thanthe size of a pellet is applied. Moreover, in a nanobeam electrondiffraction pattern of the nc-OS, regions with high luminance in acircular (ring) pattern are shown in some cases. Also in a nanobeamelectron diffraction pattern of the nc-OS, a plurality of spots is shownin a ring-like region in some cases.

Since there is no regularity of crystal orientation between the pellets(nanocrystals) as mentioned above, the nc-OS can also be referred to asan oxide semiconductor including random aligned nanocrystals (RANC) oran oxide semiconductor including non-aligned nanocrystals (NANC).

Thus, the nc-OS is an oxide semiconductor that has high regularity ascompared to an amorphous oxide semiconductor. Therefore, the nc-OS islikely to have a lower density of defect states than an a-like OS and anamorphous oxide semiconductor. Note that there is no regularity ofcrystal orientation between different pellets in the nc-OS. Therefore,the nc-OS has a higher density of defect states than the CAAC-OS.

<a-Like OS>

An a-like OS has a structure between those of the nc-OS and theamorphous oxide semiconductor.

In a high-resolution TEM image of the a-like OS film, a void may beobserved. Furthermore, in the high-resolution TEM image, there are aregion where a crystal part is clearly observed and a region where acrystal part is not observed.

The a-like OS has an unstable structure because it contains a void. Toverify that an a-like OS has an unstable structure as compared with aCAAC-OS and an nc-OS, a change in structure caused by electronirradiation is described below.

An a-like OS (referred to as a specimen A), an nc-OS (referred to as aspecimen B), and a CAAC-OS (referred to as a specimen C) are prepared asspecimens subjected to electron irradiation. Each of the specimens is anIn—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each specimen isobtained. The high-resolution cross-sectional TEM images show that allthe specimens have crystal parts.

Note that which part is regarded as a crystal part is determined asfollows. It is known that a unit cell of the InGaZnO₄ crystal has astructure in which nine layers including three In—O layers and sixGa—Zn—O layers are layered in the c-axis direction. Accordingly, thedistance between the adjacent layers is equivalent to the latticespacing on the (009) plane (also referred to as d value). The value iscalculated to be 0.29 nm from crystal structural analysis. Accordingly,a portion where the lattice spacing between lattice fringes is greaterthan or equal to 0.28 nm and less than or equal to 0.30 nm is regardedas a crystal part of InGaZnO₄. Each of lattice fringes corresponds tothe a-b plane of the InGaZnO₄ crystal.

FIG. 5 shows change in the average size of crystal parts (at 22 pointsto 45 points) in each specimen. Note that the crystal part sizecorresponds to the length of a lattice fringe. FIG. 5 indicates that thecrystal part size in the a-like OS increases with an increase in thecumulative electron dose. Specifically, as shown by (1) in FIG. 5, acrystal part of approximately 1.2 nm (also referred to as an initialnucleus) at the start of TEM observation grows to a size ofapproximately 2.6 nm at a cumulative electron dose of 4.2×10⁸ e⁻/nm². Incontrast, the crystal part size in the nc-OS and the CAAC-OS showslittle change from the start of electron irradiation to a cumulativeelectron dose of 4.2×10⁸ e⁻/nm². Specifically, as shown by (2) and (3)in FIG. 5, the average crystal sizes in an nc-OS and a CAAC-OS areapproximately 1.4 nm and approximately 2.1 nm, respectively, regardlessof the cumulative electron dose.

In this manner, growth of the crystal part in the a-like OS is inducedby electron irradiation. In contrast, in the nc-OS and the CAAC-OS,growth of the crystal part is hardly induced by electron irradiation.Therefore, the a-like OS has an unstable structure as compared with thenc-OS and the CAAC-OS.

The a-like OS has a lower density than the nc-OS and the CAAC-OS becauseit contains a void. Specifically, the density of the a-like OS is higherthan or equal to 78.6% and lower than 92.3% of the density of the singlecrystal oxide semiconductor having the same composition. The density ofeach of the nc-OS and the CAAC-OS is higher than or equal to 92.3% andlower than 100% of the density of the single crystal oxide semiconductorhaving the same composition. Note that it is difficult to deposit anoxide semiconductor having a density of lower than 78% of the density ofthe single crystal oxide semiconductor.

For example, in the case of an oxide semiconductor having an atomicratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO₄ with arhombohedral crystal structure is 6.357 g/cm³. Accordingly, in the caseof the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, thedensity of the a-like OS is higher than or equal to 5.0 g/cm³ and lowerthan 5.9 g/cm³. For example, in the case of the oxide semiconductorhaving an atomic ratio of In:Ga:Zn=1:1:1, the density of each of thenc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm³ and lowerthan 6.3 g/cm³.

Note that single crystals with the same composition do not exist in somecases. In that case, single crystal oxide semiconductors with differentcompositions are combined at an adequate ratio, which makes it possibleto calculate density equivalent to that of a single crystal oxidesemiconductor with the desired composition. The density of a singlecrystal oxide semiconductor having the desired composition can becalculated using a weighted average according to the combination ratioof the single crystal oxide semiconductors with different compositions.Note that it is preferable to use as few kinds of single crystal oxidesemiconductors as possible to calculate the density.

As described above, oxide semiconductors have various structures andvarious properties. Note that an oxide semiconductor may be a stackedlayer including two or more of an amorphous oxide semiconductor, ana-like OS, an nc-OS, and a CAAC-OS, for example.

Embodiment 2

<Deposition Method>

In this example, an example of a method of depositing a CAAC-OS film isdescribed as an example of a method of depositing an oxide according toone embodiment of the disclosed invention with reference to FIGS. 6A to6D, FIG. 7, FIGS. 8A to 8E, FIGS. 9A to 9C, and FIG. 10.

FIG. 6A is a schematic view of the inside of a deposition chamber. TheCAAC-OS can be deposited by a sputtering method.

As shown in FIG. 6A, a substrate 5220 and a target 5230 are arranged toface each other. Plasma 5240 is generated between the substrate 5220 andthe target 5230. A heating mechanism 5260 is under the substrate 5220.The target 5230 is attached to a backing plate although not shown in thedrawing. A plurality of magnets is arranged to face the target 5230 withthe backing plate positioned therebetween. A sputtering method in whichthe disposition speed is increased by utilizing a magnetic field ofmagnets is referred to as a magnetron sputtering method.

The distance d between the substrate 5220 and the target 5230 (alsoreferred to as a target-substrate distance (T-S distance)) is greaterthan or equal to 0.01 m and less than or equal to 1 m, preferablygreater than or equal to 0.02 m and less than or equal to 0.5 m. Thedeposition chamber is mostly filled with a deposition gas (e.g., anoxygen gas, an argon gas, or a mixed gas containing oxygen at 5 vol % ormore) and controlled to be higher than or equal to 0.01 Pa and lowerthan or equal to 100 Pa, preferably higher than or equal to 0.1 Pa andlower than or equal to 10 Pa. Here, discharge starts by application of avoltage at a certain value or higher to the target 5230, and plasma 5240is observed. Note that the magnetic field in the vicinity of the target5230 forms a high-density plasma region. In the high-density plasmaregion, the deposition gas is ionized, so that an ion 5201 is generated.Examples of the ion 5201 include an oxygen cation (O⁺) and an argoncation (Ar⁺).

The target 5230 has a polycrystalline structure which includes aplurality of crystal grains and in which a cleavage plane exists in anyof the crystal grains. FIG. 7 shows a crystal structure of InMZnO₄ (M isan element such as aluminum, gallium, yttrium, or tin) included in thetarget 5230 as an example. Note that the crystal structure shown in FIG.7 is InMZnO₄ observed from a direction parallel to a b-axis. In thecrystal of InMZnO₄, oxygen atoms are negatively charged, wherebyrepulsive force is generated between the two adjacent M-Zn—O layers.Thus, the InMZnO₄ crystal has a cleavage plane between the two adjacentM-Zn—O layers.

The ion 5201 generated in the high-density plasma region is acceleratedto move toward the target 5230 side by an electric field, and thencollides with the target 5230. At this time, a pellet 5200 which is aflat-plate-like or pellet-like sputtered particle is separated from thecleavage plane (see FIG. 6A). The pellet 5200 corresponds to a portionbetween the two cleavage planes shown in FIG. 7. Thus, when the pellet5200 is observed, the cross-section thereof is as shown in FIG. 6B, andthe top surface thereof is as shown in FIG. 6C. Note that structure ofthe pellet 5200 may be distorted by an impact of collision of the ion5201. Note that along with the separation of the pellet 5200, a particle5203 is also sputtered from the target 5230. The particle 5203 has anatom or an aggregate of several atoms. Therefore, the particle 5203 canbe referred to as an atomic particle.

The pellet 5200 is a flat-plate-like (pellet-like) sputtered particlehaving a triangle plane, e.g., regular triangle plane. Alternatively,the pellet 5200 is a flat-plate-like (pellet-like) sputtered particlehaving a hexagon plane, e.g., regular hexagon plane. However, the shapeof a flat plane of the pellet 5200 is not limited to a triangle or ahexagon. For example, the flat plane may have a shape formed bycombining two or more triangles. For example, a quadrangle (e.g.,rhombus) may be formed by combining two triangles (e.g., regulartriangles).

The thickness of the pellet 5200 is determined depending on the kind ofdeposition gas and the like. For example, the thickness of the pellet5200 is greater than or equal to 0.4 nm and less than or equal to 1 nm,preferably greater than or equal to 0.6 nm and less than or equal to 0.8nm. In addition, the width of the pellet 5200 is, for example, greaterthan or equal to 1 nm and less than or equal to 3 nm, preferably greaterthan or equal to 1.2 nm and less than or equal to 2.5 nm. For example,the ion 5201 collides with the target 5230 including the In-M-Zn oxide.Then, the pellet 5200 including three layers of an M-Zn—O layer, an In—Olayer, and an M-Zn—O layer is separated. Note that along with theseparation of the pellet 5200, a particle 5203 is also sputtered fromthe target 5230. The particle 5203 has an atom or an aggregate ofseveral atoms. Therefore, the particle 5203 can be referred to as anatomic particle.

The pellet 5200 may receive a charge when passing through the plasma5240, so that surfaces thereof are negatively or positively charged. Forexample, the pellet 5200 receives a negative charge from O²⁻ in theplasma 5240. As a result, oxygen atoms on the surfaces of the pellet5200 may be negatively charged. In addition, when passing through theplasma 5240, the pellet 5200 is sometimes combined with indium, theelement M, zinc, oxygen, or the like in the plasma 5240 to grow up.

The pellet 5200 and the particle 5203 that have passed through theplasma 5240 reach the surface of the substrate 5220. Note that part ofthe particle 5203 is discharged to the outside by a vacuum pump or thelike because the particle 5203 is small in mass.

Next, deposition of the pellet 5200 and the particle 5203 over thesurface of the substrate 5220 is described with reference to FIGS. 8A to8C.

First, a first of the pellets 5200 is deposited over the substrate 5220.Since the pellet 5200 has a flat-plate-like shape, it is deposited sothat the flat plane faces the surface of the substrate 5220 (FIG. 8A).Here, a charge on a surface of the pellet 5200 on the substrate 5220side is lost through the substrate 5220.

Next, a second of the pellets 5200 reaches the substrate 5220. Here,since the surface of the first of the pellets 5200 and the surface ofthe second of the pellets 5200 are charged, they repel each other (FIG.8B).

As a result, the second of the pellets 5200 avoids being deposited overthe first of the pellets 5200, and is deposited over the surface of thesubstrate 5220 so as to be a little distance away from the first of thepellets 5200 (FIG. 8C). With repetition of this, millions of the pellets5200 are deposited over the surface of the substrate 5220 to have athickness of one layer. A region where any pellet 5200 is not depositedis generated between adjacent pellets 5200.

Next, the particle 5203 reaches the surface of the substrate 5220 (FIG.8D).

The particle 5203 cannot be deposited over an active region such as thesurface of the pellet 5200. Therefore, the particle 5203 is deposited soas to fill a region where the pellets 5200 are not deposited. Theparticles 5203 grow in the horizontal (lateral) direction between thepellets 5200, thereby connecting the pellets 5200. In this way, theparticles 5203 are deposited until they fill regions where the pellets5200 are not deposited. This mechanism is similar to a depositionmechanism of an atomic layer deposition (ALD) method.

Note that there can be several mechanisms for the lateral growth of theparticles 5203 between the pellets 5200. For example, as shown in FIG.8E, the pellets 5200 can be connected from side surfaces of the firstM-Zn—O layers. In this case, after the first M-Zn—O layers makeconnection, the In—O layers and the second M-Zn—O layers are connectedin this order (the first mechanism).

Alternatively, as shown in FIG. 9A, first, the particles 5203 areconnected to the sides of the first M-Zn—O layers so that each side ofthe first M-Zn—O layer has one particle 5203. Then, as shown in FIG. 9B,the particle 5203 is connected to each side of the In—O layers. Afterthat, as shown in FIG. 9C, the particle 5203 is connected to each sideof the second M-Zn—O layers (the second mechanism). Note that theconnection can also be made by the simultaneous occurrence of thedeposition in FIGS. 9A, 9B, and 9C (the third mechanism).

As shown in the above, the above three mechanisms are considered as themechanisms of the lateral growth of the particles 5203 between thepellets 5200. However, the particles 5203 may grow up laterally betweenthe pellets 5200 by other mechanisms.

Therefore, even when the orientations of a plurality of pellets 5200 aredifferent from each other, generation of crystal boundaries can besuppressed since the particles 5203 laterally grow to fill gaps betweenthe plurality of pellets 5200. In addition, as the particles 5203 makesmooth connection between the plurality of pellets 5200, a crystalstructure different from a single crystal and a polycrystal is formed.In other words, a crystal structure including distortion between minutecrystal regions (pellets 5200) is formed. The regions filling the gapsbetween the crystal regions are distorted crystal regions, and thus, itwill be not appropriate to say that the regions have an amorphousstructure.

When the particles 5203 completely fill the regions between the pellets5200, a first layer with a thickness almost the same as that of thepellet 5200 is formed. Then, a new first of the pellets 5200 isdeposited over the first layer, and a second layer is formed. Withrepetition of this cycle, the stacked-layer thin film structure isformed (FIG. 6D).

A deposition way of the pellets 5200 changes depending on the surfacetemperature of the substrate 5220 or the like. For example, if thesurface temperature of the substrate 5220 is high, migration of thepellets 5200 occurs over the substrate 5220. As a result, a proportionof the pellets 5200 that are directly connected with each other withoutthe particles 5203 increases, whereby a CAAC-OS with high orientation ismade. The surface temperature of the substrate 5220 for the depositionof the CAAC-OS is higher than or equal to 100° C. and lower than 500°C., preferably higher than or equal to 140° C. and lower than 450° C.,or further preferably higher than or equal to 170° C. and lower than400° C. Therefore, even when a large-sized substrate of the 8thgeneration or more is used as the substrate 5220, a warp or the likehardly occurs.

On the other hand, if the surface temperature of the substrate 5220 islow, the migration of the pellets 5200 over the substrate 5220 does noteasily occur. As a result, the pellets 5200 overlap with each other,whereby a nanocrystalline oxide semiconductor (nc-OS) with loworientation or the like is made (see FIG. 10). In the nc-OS, the pellets5200 are deposited with certain gaps because the pellets 5200 arenegatively charged. Therefore, the nc-OS film has low orientation butsome regularity, and thus it has a denser structure than an amorphousoxide semiconductor.

When gaps between the pellets are extremely small in a CAAC-OS, thepellets may form a large pellet. The inside of the large pellet has asingle crystal structure. For example, the size of the pellet may begreater than or equal to 10 nm and less than or equal to 200 nm, greaterthan or equal to 15 nm and less than or equal to 100 nm, or greater thanor equal to 20 nm and less than or equal to 50 nm, when seen from theabove.

According to such a model, the pellets 5200 are considered to bedeposited on the surface of the substrate 5220. Thus, a CAAC-OS can bedeposited even when a formation surface does not have a crystalstructure; therefore, a growth mechanism in this case is different fromepitaxial growth. In addition, uniform deposition of a CAAC-OS or annc-OS can be performed even over a large-sized glass substrate or thelike. For example, even when the surface of the substrate 5220(formation surface) has an amorphous structure (e.g., such as amorphoussilicon oxide), a CAAC-OS can be deposited.

Furthermore, it is found that the pellets 5200 are arranged inaccordance with a surface shape of the substrate 5220 that is thedeposition surface even when the deposition surface has unevenness.

Embodiment 3

<Transistors>

In this embodiment, transistors according to one embodiment of thedisclosed invention are described with reference to FIG. 11, FIGS. 12Aand 12B, FIGS. 13A and 13B, FIGS. 14A and 14B, and FIGS. 15A and 15B.

Transistors according to one embodiment of the present invention eachpreferably include the above-described nc-OS or CAAC-OS.

<Transistor Structure 1>

FIGS. 12A and 12B are a top view and a cross-sectional view whichillustrate a transistor of one embodiment of the present invention. FIG.12A is a top view and FIG. 12B is a cross-sectional view taken alongdashed-dotted line A1-A2 and dashed-dotted line A3-A4 in FIG. 12A. Notethat for simplification of the drawing, some components are notillustrated in the top view in FIG. 12A.

The transistor in FIGS. 12A and 12B includes a conductor 413 over asubstrate 400, an insulator 402 having a projection over the substrate400 and the conductor 413, an insulator 406 a over the projection of theinsulator 402, a semiconductor 406 b over the insulator 406 a, aconductor 416 a and a conductor 416 b which are in contact with a topsurface and a side surface of the semiconductor 406 b and which arearranged to be separated from each other, an insulator 406 c over thesemiconductor 406 b, the conductor 416 a, and the conductor 416 b, aninsulator 412 over the insulator 406 c, a conductor 404 over theinsulator 412, an insulator 408 over the conductor 416 a, the conductor416 b, and the conductor 404, and an insulator 418 over the insulator408. Although the conductor 413 is part of the transistor here, atransistor structure of one embodiment of the present invention is notlimited thereto. For example, the conductor 413 may be a componentindependent of the transistor.

Note that the insulator 406 c is in contact with at least a top surfaceand a side surface of the semiconductor 406 b in the cross section takenalong line A3-A4. Furthermore, the conductor 404 faces the top surfaceand the side surface of the semiconductor 406 b with the insulator 406 cand the insulator 412 provided therebetween in the cross section takenalong line A3-A4. The conductor 413 faces a bottom surface of thesemiconductor 406 b with the insulator 402 provided therebetween. Theinsulator 402 does not necessarily include a projection. The insulator406 c, the insulator 408, and/or the insulator 418 is not necessarilyprovided.

The semiconductor 406 b serves as a channel formation region of thetransistor. The conductor 404 serves as a first gate electrode (alsoreferred to as a front gate electrode) of the transistor. The conductor413 serves as a second gate electrode (also referred to as a back gateelectrode) of the transistor. The conductor 416 a and the conductor 416b serve as a source electrode and a drain electrode of the transistor.The insulator 408 functions as a barrier layer. The insulator 408 has,for example, a function of blocking oxygen and/or hydrogen.Alternatively, the insulator 408 has, for example, a higher capabilityof blocking oxygen and/or hydrogen than the insulator 406 a and/or theinsulator 406 c.

Note that the insulator 406 a or the insulator 406 c is categorized as asemiconductor in some cases depending on which of the materialsdescribed later is used and the ratio between the materials. Since thesemiconductor 406 b serves as a channel formation region of thetransistor as described above, carriers do not move in the insulator 406a and the insulator 406 c in some cases. Thus, even when the insulator406 a or the insulator 406 c has semiconductor properties, it isreferred to as an insulator in this embodiment.

The insulator 402 is preferably an insulator containing excess oxygen.

The insulator containing excess oxygen means an insulator from whichoxygen is released by heat treatment, for example. The silicon oxidelayer containing excess oxygen means a silicon oxide layer which canrelease oxygen by heat treatment or the like, for example. Therefore,the insulator 402 is an insulator in which oxygen can be moved. In otherwords, the insulator 402 may be an insulator having anoxygen-transmitting property. For example, the insulator 402 may be aninsulator having a higher oxygen-transmitting property than theinsulator 406 a.

The insulator containing excess oxygen has a function of reducing oxygenvacancies in the semiconductor 406 b in some cases. Such oxygenvacancies form DOS in the semiconductor 406 b and serve as hole traps orthe like. In addition, hydrogen comes into the site of such an oxygenvacancy and forms an electron serving as a carrier. Therefore, byreducing the oxygen vacancies in the semiconductor 406 b, the transistorcan have stable electrical characteristics.

Here, an insulator from which oxygen is released by heat treatment mayrelease oxygen, the amount of which is higher than or equal to 1×10¹⁸atoms/cm³, higher than or equal to 1×10¹⁹ atoms/cm³, or higher than orequal to 1×10²⁰ atoms/cm³ (converted into the number of oxygen atoms) inthermal desorption spectroscopy (TDS) analysis in the range of a surfacetemperature of 100° C. to 700° C. or 100° C. to 500° C.

Here, the method of measuring the amount of released oxygen using TDSanalysis is described below.

The total amount of released gas from a measurement specimen in TDSanalysis is proportional to the integral value of the ion intensity ofthe released gas. Then, comparison with a reference specimen is made,whereby the total amount of released gas can be calculated.

For example, the number of released oxygen molecules (N_(O2)) from ameasurement specimen can be calculated according to the followingformula using the TDS results of a silicon substrate containing hydrogenat a predetermined density, which is a reference specimen, and the TDSresults of the measurement specimen. Here, all gases having amass-to-charge ratio of 32 which are obtained in the TDS analysis areassumed to originate from an oxygen molecule. Note that CH₃OH, which isa gas having the mass-to-charge ratio of 32, is not taken intoconsideration because it is unlikely to be present. Furthermore, anoxygen molecule including an oxygen atom having a mass number of 17 or18 which is an isotope of an oxygen atom is also not taken intoconsideration because the proportion of such a molecule in the naturalworld is minimal.N _(O2) =N _(H2) /S _(H2) ×S _(O2)×α

The value N_(H2) is obtained by conversion of the amount of hydrogenmolecules desorbed from the standard specimen into densities. The valueS_(H2) is the integral value of ion intensity in the case where thestandard specimen is subjected to the TDS analysis. Here, the referencevalue of the standard specimen is set to N_(H2)/S_(H2). S_(O2) is theintegral value of ion intensity when the measurement specimen isanalyzed by TDS. The value a is a coefficient affecting the ionintensity in the TDS analysis. Refer to Patent Document 5 for details ofthe above formula. The amount of released oxygen was measured with athermal desorption spectroscopy apparatus produced by ESCO Ltd.,EMD-WA1000S/W using a silicon substrate containing hydrogen atoms at1×10¹⁶ atoms/cm² as the reference specimen.

Furthermore, in the TDS analysis, oxygen is partly detected as an oxygenatom. The ratio between oxygen molecules and oxygen atoms can becalculated from the ionization rate of the oxygen molecules. Note that,since the above a includes the ionization rate of the oxygen molecules,the amount of the released oxygen atoms can also be estimated throughthe evaluation of the amount of the released oxygen molecules.

Note that N_(O2) is the amount of the released oxygen molecules. Theamount of released oxygen in the case of being converted into oxygenatoms is twice the amount of the released oxygen molecules.

Furthermore, the insulator from which oxygen is released by heattreatment may contain a peroxide radical. Specifically, the spin densityattributed to the peroxide radical is greater than or equal to 5×10¹⁷spins/cm³. Note that the insulator containing a peroxide radical mayhave an asymmetric signal with a g factor of approximately 2.01 inelectron spin resonance (ESR).

The insulator containing excess oxygen may be formed using oxygen-excesssilicon oxide (SiO_(X) (X>2)). In the oxygen-excess silicon oxide(SiO_(X) (X>2)), the number of oxygen atoms per unit volume is more thantwice the number of silicon atoms per unit volume. The number of siliconatoms and the number of oxygen atoms per unit volume are measured byRutherford backscattering spectrometry (RBS).

As illustrated in FIG. 12B, the side surfaces of the semiconductor 406 bare in contact with the conductor 416 a and the conductor 416 b. Thesemiconductor 406 b can be electrically surrounded by an electric fieldof the conductor 404 (a structure in which a semiconductor iselectrically surrounded by an electric field of a conductor is referredto as a surrounded channel (s-channel) structure). Therefore, a channelis formed in the entire semiconductor 406 b (bulk) in some cases. In thes-channel structure, a large amount of current can flow between a sourceelectrode and a drain electrode of a transistor, so that a high on-statecurrent can be obtained.

The s-channel structure is suitable for a miniaturized transistorbecause a high on-state current can be obtained. A semiconductor deviceincluding the miniaturized transistor can have a high integration degreeand high density. For example, the channel length of the transistor ispreferably less than or equal to 40 nm, further preferably less than orequal to 30 nm, still further preferably less than or equal to 20 nm andthe channel width of the transistor is preferably less than or equal to40 nm, further preferably less than or equal to 30 nm, still furtherpreferably less than or equal to 20 nm.

Furthermore, by applying a lower voltage or a higher voltage than asource electrode to the conductor 413, the threshold voltage of thetransistor may be shifted in the positive direction or the negativedirection. For example, by shifting the threshold voltage of thetransistor in the positive direction, a normally-off transistor in whichthe transistor is in a non-conduction state (off state) even when thegate voltage is 0 V can be achieved in some cases. The voltage appliedto the conductor 413 may be a variable or a fixed voltage. When thevoltage applied to the conductor 413 is a variable, a circuit forcontrolling the voltage may be electrically connected to the conductor413.

Next, a semiconductor and an insulator which can be used as theinsulator 406 a, the semiconductor 406 b, the insulator 406 c, or thelike is described below.

The semiconductor 406 b is an oxide semiconductor containing indium, forexample. An oxide semiconductor can have high carrier mobility (electronmobility) by containing indium, for example. The semiconductor 406 bpreferably contains an element M. The element M is preferably aluminum,gallium, yttrium, tin, or the like. Other elements which can be used asthe element M are boron, silicon, titanium, iron, nickel, germanium,zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum,tungsten, and the like. Note that two or more of the above elements maybe used in combination as the element M. The element M is an elementhaving a high bonding energy with oxygen, for example. The element M isan element whose bonding energy with oxygen is higher than that ofindium. The element M is an element that can increase the energy gap ofthe oxide semiconductor, for example. Furthermore, the semiconductor 406b preferably contains zinc. When the oxide semiconductor contains zinc,the oxide semiconductor is easily to be crystallized, for example.

Note that the semiconductor 406 b is not limited to the oxidesemiconductor containing indium. The semiconductor 406 b may be, forexample, an oxide semiconductor which does not contain indium andcontains zinc, an oxide semiconductor which does not contain indium andcontains gallium, or an oxide semiconductor which does not containindium and contains tin, e.g., a zinc tin oxide or a gallium tin oxide.

For the semiconductor 406 b, an oxide with a wide energy gap may beused. For example, the energy gap of the semiconductor 406 b is greaterthan or equal to 2.5 eV and less than or equal to 4.2 eV, preferablygreater than or equal to 2.8 eV and less than or equal to 3.8 eV,further preferably greater than or equal to 3 eV and less than or equalto 3.5 eV.

For example, the insulator 406 a and the insulator 406 c include one ormore elements other than oxygen included in the semiconductor 406 b.Since the insulator 406 a and the insulator 406 c each include one ormore elements other than oxygen included in the semiconductor 406 b, aninterface state is less likely to be formed at the interface between theinsulator 406 a and the semiconductor 406 b and the interface betweenthe semiconductor 406 b and the insulator 406 c.

The insulator 406 a, the semiconductor 406 b, and the insulator 406 cpreferably include at least indium. In the case of using an In-M-Znoxide as the insulator 406 a, when a summation of In and M is assumed tobe 100 atomic %, the proportions of In and Mare preferably set to beless than 50 atomic % and greater than 50 atomic %, respectively,further preferably less than 25 atomic % and greater than 75 atomic %,respectively. In the case of using an In-M-Zn oxide as the semiconductor406 b, when the summation of In and M is assumed to be 100 atomic %, theproportions of In and M are preferably set to be greater than 25 atomic% and less than 75 atomic %, respectively, further preferably greaterthan 34 atomic % and less than 66 atomic %, respectively. In the case ofusing an In-M-Zn oxide as the insulator 406 c, when the summation of Inand M is assumed to be 100 atomic %, the proportions of In and Marepreferably set to be less than 50 atomic % and greater than 50 atomic %,respectively, further preferably less than 25 atomic % and greater than75 atomic %, respectively. Note that the insulator 406 c may be an oxidethat is a type the same as that of the insulator 406 a. Note that theinsulator 406 a and/or the insulator 406 c do/does not necessarilycontain indium in some cases. For example, the insulator 406 a and/orthe insulator 406 c may be gallium oxide.

As the semiconductor 406 b, an oxide having an electron affinity higherthan those of the insulators 406 a and 406 c is used. For example, asthe semiconductor 406 b, an oxide having an electron affinity higherthan those of the insulators 406 a and 406 c by 0.07 eV or higher and1.3 eV or lower, preferably 0.1 eV or higher and 0.7 eV or lower,further preferably 0.15 eV or higher and 0.4 eV or lower is used. Notethat the electron affinity refers to an energy gap between the vacuumlevel and the bottom of the conduction band.

An indium gallium oxide has a small electron affinity and a highoxygen-blocking property. Therefore, the insulator 406 c preferablyincludes an indium gallium oxide. The gallium atomic ratio [Ga/(In+Ga)]is, for example, higher than or equal to 70%, preferably higher than orequal to 80%, further preferably higher than or equal to 90%.

Note that the composition of the insulator 406 a is preferably in theneighborhood of the composition represented by the bold line in FIG. 11.The composition of the semiconductor 406 b is preferably in theneighborhood of the composition represented by the bold line in FIG. 11.The composition of the insulator 406 c is preferably in the neighborhoodof the composition represented by the bold line in FIG. 11. When thesecompositions are employed, the channel formation region of thetransistor can have a single crystal structure. Alternatively, thechannel formation region, the source region, and the drain region of thetransistor can have a single crystal structure in some cases. When thechannel formation region of the transistor has a single crystalstructure, the transistor can have high frequency characteristics insome cases.

At this time, when a gate voltage is applied, a channel is formed in thesemiconductor 406 b having the highest electron affinity in theinsulator 406 a, the semiconductor 406 b, and the insulator 406 c.

Here, in some cases, there is a mixed region of the insulator 406 a andthe semiconductor 406 b between the insulator 406 a and thesemiconductor 406 b. Furthermore, in some cases, there is a mixed regionof the semiconductor 406 b and the insulator 406 c between thesemiconductor 406 b and the insulator 406 c. The mixed region has a lowdensity of interface states. For that reason, the stack of the insulator406 a, the semiconductor 406 b, and the insulator 406 c has a bandstructure where energy at each interface and in the vicinity of theinterface is changed continuously (continuous junction).

At this time, electrons move mainly in the semiconductor 406 b, not inthe insulator 406 a and the insulator 406 c. As described above, whenthe interface state density at the interface between the insulator 406 aand the semiconductor 406 b and the interface state density at theinterface between the semiconductor 406 b and the insulator 406 c aredecreased, electron movement in the semiconductor 406 b is less likelyto be inhibited and the on-state current of the transistor can beincreased.

As factors of inhibiting electron movement are decreased, the on-statecurrent of the transistor can be increased. For example, in the casewhere there is no factor of inhibiting electron movement, electrons areassumed to be moved efficiently. Electron movement is inhibited, forexample, in the case where physical unevenness in a channel formationregion is large.

To increase the on-state current of the transistor, for example, rootmean square (RMS) roughness with a measurement area of 1 μm×1 μm of atop surface or a bottom surface of the semiconductor 406 b (a formationsurface; here, the insulator 406 a) is less than 1 nm, preferably lessthan 0.6 nm, further preferably less than 0.5 nm, still furtherpreferably less than 0.4 nm. The average surface roughness (alsoreferred to as Ra) with the measurement area of 1 μm×1 μm is less than 1nm, preferably less than 0.6 nm, further preferably less than 0.5 nm,still further preferably less than 0.4 nm. The maximum difference (P−V)with the measurement area of 1 μm×1 μm is less than 10 nm, preferablyless than 9 nm, further preferably less than 8 nm, still furtherpreferably less than 7 nm. RMS roughness, Ra, and P−V can be measuredusing a scanning probe microscope SPA-500 manufactured by SII NanoTechnology Inc.

The electron movement is also inhibited, for example, in the case wherethe density of defect states is high in a region where a channel isformed.

For example, in the case where the semiconductor 406 b contains oxygenvacancies (V_(O)), an elemental hydrogen, a hydrogen molecule, ahydrogen atom, or a hydrogen ion (also collectively referred to ashydrogen in this specification) might enter sites of the oxygenvacancies to form a donor level (hereinafter, hydrogen entering thesites of oxygen vacancies are also referred to as V_(O)H). BecauseV_(O)H scatters electrons, it is a factor of decreasing the on-statecurrent of the transistor. Note that the sites of oxygen vacanciesbecome more stable by entry of oxygen than by entry of hydrogen. Thus,by decreasing oxygen vacancies in the semiconductor 406 b, the on-statecurrent of the transistor can be increased in some cases.

To decrease oxygen vacancies in the semiconductor 406 b, for example,there is a method in which excess oxygen in the insulator 402 is movedto the semiconductor 406 b through the insulator 406 a. In this case,the insulator 406 a is preferably a layer having an oxygen-transmittingproperty (a layer through which oxygen passes or is transmitted).

In the case where the transistor has an s-channel structure, a channelis formed in the whole of the semiconductor 406 b. Therefore, as thesemiconductor 406 b has a larger thickness, a channel region becomeslarger. In other words, the thicker the semiconductor 406 b is, thelarger the on-state current of the transistor is. For example, thesemiconductor 406 b has a region with a thickness greater than or equalto 10 nm, preferably greater than or equal to 20 nm, more preferablygreater than or equal to 40 nm, further preferably greater than or equalto 60 nm, still further preferably greater than or equal to 100 nm. Notethat the semiconductor 406 b has a region with a thickness, for example,less than or equal to 300 nm, preferably less than or equal to 200 nm,further preferably less than or equal to 150 nm because the productivityof the semiconductor device might be decreased. In some cases, when thechannel formation region is reduced in size, the electricalcharacteristics of the transistor are improved. Therefore, thesemiconductor 406 b may have a thickness less than 10 nm.

Moreover, the thickness of the insulator 406 c is preferably as small aspossible to increase the on-state current of the transistor. Thethickness of the insulator 406 c is less than 10 nm, preferably lessthan or equal to 5 nm, more preferably less than or equal to 3 nm, forexample. Meanwhile, the insulator 406 c has a function of blocking entryof elements other than oxygen (such as hydrogen and silicon) included inthe adjacent insulator into the semiconductor 406 b where a channel isformed. For this reason, it is preferable that the insulator 406 c havea certain thickness. The thickness of the insulator 406 c is greaterthan or equal to 0.3 nm, preferably greater than or equal to 1 nm,further preferably greater than or equal to 2 nm, for example. Theinsulator 406 c preferably has an oxygen blocking property to suppressoutward diffusion of oxygen released from the insulator 402 and thelike.

To improve reliability, preferably, the thickness of the insulator 406 ais large and the thickness of the insulator 406 c is small. For example,the insulator 406 a has a region with a thickness, for example, greaterthan or equal to 10 nm, preferably greater than or equal to 20 nm,further preferably greater than or equal to 40 nm, still furtherpreferably greater than or equal to 60 nm. When the thickness of theinsulator 406 a is made large, a distance from an interface between theadjacent insulator and the insulator 406 a to the semiconductor 406 b inwhich a channel is formed can be large. Since the productivity of thesemiconductor device might be decreased, the insulator 406 a has aregion with a thickness, for example, less than or equal to 200 nm,preferably less than or equal to 120 nm, further preferably less than orequal to 80 nm.

For example, a region in which the concentration of silicon which ismeasured by secondary ion mass spectrometry (SIMS) is lower than 1×10¹⁹atoms/cm³, preferably lower than 5×10¹⁸ atoms/cm³, or further preferablylower than 2×10¹⁸ atoms/cm³ is provided between the semiconductor 406 band the insulator 406 a. A region with a silicon concentration lowerthan 1×10¹⁹ atoms/cm³, preferably lower than 5×10¹⁸ atoms/cm³, furtherpreferably lower than 2×10¹⁸ atoms/cm³ which is measured by SIMS isprovided between the semiconductor 406 b and the insulator 406 c.

It is preferable to reduce the concentration of hydrogen in theinsulator 406 a and the insulator 406 c in order to reduce theconcentration of hydrogen in the semiconductor 406 b. The insulator 406a and the insulator 406 c each have a region in which the concentrationof hydrogen measured by SIMS is lower than or equal to 2×10²⁰ atoms/cm³,preferably lower than or equal to 5×10¹⁹ atoms/cm³, further preferablylower than or equal to 1×10¹⁹ atoms/cm³, still further preferably lowerthan or equal to 5×10¹⁸ atoms/cm³. It is preferable to reduce theconcentration of nitrogen in the insulator 406 a and the insulator 406 cin order to reduce the concentration of nitrogen in the semiconductor406 b. The insulator 406 a and the insulator 406 c each have a region inwhich the concentration of nitrogen measured by SIMS is lower than5×10¹⁹ atoms/cm³, preferably lower than or equal to 5×10¹⁸ atoms/cm³,further preferably lower than or equal to 1×10¹⁸ atoms/cm³, stillfurther preferably lower than or equal to 5×10¹⁷ atoms/cm³.

The above three-layer structure is an example. For example, a two-layerstructure without the insulator 406 a or the insulator 406 c may beemployed. Alternatively, a four-layer structure in which any one of thesemiconductors described as examples of the insulator 406 a, thesemiconductor 406 b, and the insulator 406 c is provided below or overthe insulator 406 a or below or over the insulator 406 c may beemployed. Alternatively, an n-layer structure (n is an integer of 5 ormore) in which any one of the semiconductors described as examples ofthe insulator 406 a, the semiconductor 406 b, and the insulator 406 c isprovided at two or more of the following positions: over the insulator406 a, below the insulator 406 a, over the insulator 406 c, and belowthe insulator 406 c.

As the substrate 400, an insulator substrate, a semiconductor substrate,or a conductor substrate may be used, for example. As the insulatorsubstrate, a glass substrate, a quartz substrate, a sapphire substrate,a stabilized zirconia substrate (e.g., an yttria-stabilized zirconiasubstrate), or a resin substrate is used, for example. As thesemiconductor substrate, a single material semiconductor substrate ofsilicon, germanium, or the like or a compound semiconductor substratecontaining silicon carbide, silicon germanium, gallium arsenide, indiumphosphide, zinc oxide, or gallium oxide as a material is used, forexample. A semiconductor substrate in which an insulator region isprovided in the above semiconductor substrate, e.g., a silicon oninsulator (SOI) substrate or the like is used. As the conductorsubstrate, a graphite substrate, a metal substrate, an alloy substrate,a conductive resin substrate, or the like is used. A substrate includinga metal nitride, a substrate including a metal oxide, or the like isused. An insulator substrate provided with a conductor or asemiconductor, a semiconductor substrate provided with a conductor or aninsulator, a conductor substrate provided with a semiconductor or aninsulator, or the like is used. Alternatively, any of these substratesover which an element is provided may be used. As the element providedover the substrate, a capacitor, a resistor, a switching element, alight-emitting element, a memory element, or the like is used.

Alternatively, a flexible substrate may be used as the substrate 400. Asa method of providing the transistor over a flexible substrate, there isa method in which the transistor is formed over a non-flexible substrateand then the transistor is separated and transferred to the substrate400 which is a flexible substrate. In that case, a separation layer ispreferably provided between the non-flexible substrate and thetransistor. As the substrate 400, a sheet, a film, or a foil containinga fiber may be used. The substrate 400 may have elasticity. Thesubstrate 400 may have a property of returning to its original shapewhen bending or pulling is stopped. Alternatively, the substrate 400 mayhave a property of not returning to its original shape. The thickness ofthe substrate 400 is, for example, greater than or equal to 5 μm andless than or equal to 700 μm, preferably greater than or equal to 10 μmand less than or equal to 500 μm, or further preferably greater than orequal to 15 μm and less than or equal to 300 μm. When the substrate 400has a small thickness, the weight of the semiconductor device can bereduced. When the substrate 400 has a small thickness, even in the caseof using glass or the like, the substrate 400 may have elasticity or aproperty of returning to its original shape when bending or pulling isstopped. Therefore, an impact applied to the semiconductor device overthe substrate 400, which is caused by dropping or the like, can bereduced. That is, a durable semiconductor device can be provided.

For the substrate 400 which is a flexible substrate, metal, an alloy,resin, glass, or fiber thereof can be used, for example. The flexiblesubstrate 400 preferably has a lower coefficient of linear expansionbecause deformation due to an environment is suppressed. The flexiblesubstrate 400 is formed using, for example, a material whose coefficientof linear expansion is lower than or equal to 1×10⁻³/K, lower than orequal to 5×10⁻⁵/K, or lower than or equal to 1×10⁻⁵/K. Examples of theresin include polyester, polyolefin, polyamide (e.g., nylon or aramid),polyimide, polycarbonate, and acrylic. In particular, aramid ispreferably used for the flexible substrate 400 because of its lowcoefficient of linear expansion.

The conductor 413 may be formed to have a single-layer structure or astacked-layer structure using a conductor containing one or more kindsof boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum,titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium,yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin,tantalum, and tungsten, for example. An alloy or a compound of the aboveelement may be used, for example, and a conductor containing aluminum, aconductor containing copper and titanium, a conductor containing copperand manganese, a conductor containing indium, tin, and oxygen, aconductor containing titanium and nitrogen, or the like may be used.

The insulator 402 may be formed to have, for example, a single-layerstructure or a stacked-layer structure including an insulator containingboron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon,phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium,lanthanum, neodymium, hafnium, or tantalum. The insulator 402 may beformed using aluminum oxide, magnesium oxide, silicon oxide, siliconoxynitride, silicon nitride oxide, silicon nitride, gallium oxide,germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide,neodymium oxide, hafnium oxide, or tantalum oxide.

The insulator 402 may have a function of preventing diffusion ofimpurities from the substrate 400. In the case where the semiconductor406 b is an oxide semiconductor, the insulator 402 can have a functionof supplying oxygen to the semiconductor 406 b.

Each of the conductor 416 a and the conductor 416 b may be formed tohave, for example, a single-layer structure or a stacked-layer structureincluding a conductor containing one or more kinds of boron, nitrogen,oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium,manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium,molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. Analloy or a compound of the above element may be used, for example, and aconductor containing aluminum, a conductor containing copper andtitanium, a conductor containing copper and manganese, a conductorcontaining indium, tin, and oxygen, a conductor containing titanium andnitrogen, or the like may be used.

Due to the conductor 416 a and the conductor 416 b, a defect may beformed in the insulator 406 a, the semiconductor 406 b, or the insulator406 c in some cases. The defect makes the insulator 406 a, thesemiconductor 406 b, or the insulator 406 c an n-type semiconductor insome cases. As a result, ohmic contact is made between any of theinsulator 406 a, the semiconductor 406 b, or the insulator 406 c and theconductor 416 a and the conductor 416 b. For example, in the case wherethe defect formed in the insulator 406 a, the semiconductor 406 b, orthe insulator 406 c is reduced by dehydrogenation or supplying excessoxygen, a Schottky junction is made between any of the insulator 406 a,the semiconductor 406 b, or the insulator 406 c and the conductor 416 aand the conductor 416 b.

The insulator 412 may be formed to have, for example, a single-layerstructure or a stacked-layer structure including an insulator containingboron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon,phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium,lanthanum, neodymium, hafnium, or tantalum. The insulator 412 may beformed using aluminum oxide, magnesium oxide, silicon oxide, siliconoxynitride, silicon nitride oxide, silicon nitride, gallium oxide,germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide,neodymium oxide, hafnium oxide, or tantalum oxide.

The conductor 404 may be formed to have, for example, a single-layerstructure or a stacked-layer structure including a conductor containingone or more kinds of boron, nitrogen, oxygen, fluorine, silicon,phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel,copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium,silver, indium, tin, tantalum, and tungsten. An alloy or a compound ofthe above element may be used, for example, and a conductor containingaluminum, a conductor containing copper and titanium, a conductorcontaining copper and manganese, a conductor containing indium, tin, andoxygen, a conductor containing titanium and nitrogen, or the like may beused.

The insulator 408 may be formed to have, for example, a single-layerstructure or a stacked-layer structure including an insulator containingboron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon,phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium,lanthanum, neodymium, hafnium, or tantalum. The insulator 408 may bepreferably formed to have, for example, a single-layer structure or astacked-layer structure including an insulator containing aluminumoxide, silicon nitride oxide, silicon nitride, gallium oxide, yttriumoxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide,or tantalum oxide.

The insulator 418 may be formed to have, for example, a single-layerstructure or a stacked-layer structure including an insulator containingboron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon,phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium,lanthanum, neodymium, hafnium, or tantalum. The insulator 418 may beformed using, for example, aluminum oxide, magnesium oxide, siliconoxide, silicon oxynitride, silicon nitride oxide, silicon nitride,gallium oxide, germanium oxide, yttrium oxide, zirconium oxide,lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide.

Although FIGS. 12A and 12B show an example where the conductor 404 whichis a first gate electrode of a transistor is not electrically connectedto the conductor 413 which is a second gate electrode, a transistorstructure of one embodiment of the present invention is not limitedthereto. For example, as illustrated in FIG. 13A, the conductor 404 maybe electrically connected to the conductor 413. With such a structure,the conductor 404 and the conductor 413 are supplied with the samepotential; thus, switching characteristics of the transistor can beimproved. Alternatively, as illustrated in FIG. 13B, the conductor 413is not necessarily provided.

FIG. 14A is an example of a top view of a transistor. FIG. 14B is anexample of a cross-sectional view taken along dashed-dotted line F1-F2and dashed-dotted line F3-F4 in FIG. 14A. Note that some components suchas an insulator are omitted in FIG. 14A for easy understanding.

Although FIGS. 12A and 12B and the like show an example where theconductor 416 a and the conductor 416 b which function as a sourceelectrode and a drain electrode are in contact with a top surface and aside surface of the semiconductor 406 b, a top surface of the insulator402, and the like, a transistor structure of one embodiment of thepresent invention is not limited thereto. For example, as illustrated inFIGS. 14A and 14B, the conductor 416 a and the conductor 416 b may be incontact with only the top surface of the semiconductor 406 b.

As illustrated in FIG. 14B, an insulator 428 may be provided over theinsulator 418. The insulator 428 preferably has a flat top surface. Theinsulator 428 may be formed to have, for example, a single-layerstructure or a stacked-layer structure including an insulator containingboron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon,phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium,lanthanum, neodymium, hafnium, or tantalum. The insulator 428 may beformed using aluminum oxide, magnesium oxide, silicon oxide, siliconoxynitride, silicon nitride oxide, silicon nitride, gallium oxide,germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide,neodymium oxide, hafnium oxide, or tantalum oxide. To planarize the topsurface of the insulator 428, planarization treatment may be performedby a chemical mechanical polishing (CMP) method or the like.

A resin may be used as the insulator 428. For example, a resincontaining polyimide, polyamide, acrylic, silicone, or the like may beused. The use of a resin does not need planarization treatment performedon the top surface of the insulator 428 in some cases. By using a resin,a thick film can be formed in a short time; thus, the productivity canbe increased.

As illustrated in FIGS. 14A and 14B, a conductor 424 a and a conductor424 b may be provided over the insulator 428. The conductor 424 a andthe conductor 424 b may function as wirings, for example. The insulator428 may include an opening and the conductor 416 a and the conductor 424a may be electrically connected to each other through the opening. Theinsulator 428 may have another opening and the conductor 416 b and theconductor 424 b may be electrically connected to each other through theopening. In this case, the conductor 426 a and the conductor 426 b maybe provided in the respective openings.

Each of the conductor 424 a and the conductor 424 b may be formed tohave, for example, a single-layer structure or a stacked-layer structureincluding a conductor containing one or more kinds of boron, nitrogen,oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium,manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium,molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. Analloy or a compound of the above element may be used, for example, and aconductor containing aluminum, a conductor containing copper andtitanium, a conductor containing copper and manganese, a conductorcontaining indium, tin, and oxygen, a conductor containing titanium andnitrogen, or the like may be used.

In the transistor illustrated in FIGS. 14A and 14B, the conductor 416 aand the conductor 416 b are not in contact with side surfaces of thesemiconductor 406 b. Thus, an electric field applied from the conductor404 functioning as a first gate electrode to the side surfaces of thesemiconductor 406 b is less likely to be blocked by the conductor 416 aand the conductor 416 b. The conductor 416 a and the conductor 416 b arenot in contact with a top surface of the insulator 402. Thus, excessoxygen (oxygen) released from the insulator 402 is not consumed tooxidize the conductor 416 a and the conductor 416 b. Accordingly, excessoxygen (oxygen) released from the insulator 402 can be efficiently usedto reduce oxygen vacancies in the semiconductor 406 b. In other words,the transistor having the structure illustrated in FIGS. 14A and 14B hasexcellent electrical characteristics such as a high on-state current,high field-effect mobility, a small subthreshold swing value, and highreliability.

FIGS. 15A and 15B are a top view and a cross-sectional view whichillustrate a transistor of one embodiment of the present invention. FIG.15A is a top view and FIG. 15B is a cross-sectional view taken alongdashed-dotted line G1-G2 and dashed-dotted line G3-G4 in FIG. 15A. Notethat for simplification of the drawing, some components are notillustrated in the top view in FIG. 15A.

The transistor may have a structure in which, as illustrated in FIGS.15A and 15B, the conductor 416 a and the conductor 416 b are notprovided and the conductor 426 a and the conductor 426 b are in contactwith the semiconductor 406 b. In this case, a low-resistance region 423a (low-resistance region 423 b) is preferably provided in a region incontact with at least the conductor 426 a and the conductor 426 b in thesemiconductor 406 b and/or the insulator 406 a. The low-resistanceregion 423 a and the low-resistance region 423 b may be formed in such amanner that, for example, the conductor 404 and the like are used asmasks and impurities are added to the semiconductor 406 b and/or theinsulator 406 a. The conductor 426 a and the conductor 426 b may beprovided in holes (portions which penetrate) or recessed portions(portions which do not penetrate) of the semiconductor 406 b. When theconductor 426 a and the conductor 426 b are provided in holes orrecessed portions of the semiconductor 406 b, contact areas between theconductors 426 a and 426 b and the semiconductor 406 b are increased;thus, the adverse effect of the contact resistance can be decreased. Inother words, the on-state current of the transistor can be increased.

<Transistor Structure 2>

FIGS. 16A and 16B are a top view and a cross-sectional view of atransistor of one embodiment of the present invention. FIG. 16A is a topview and FIG. 16B is a cross-sectional view taken along dashed-dottedline J1-J2 and dashed-dotted line J3-J4 in FIG. 16A. Note that forsimplification of the drawing, some components are not illustrated inthe top view in FIG. 16A.

The transistor in FIGS. 16A and 16B includes a conductor 604 over asubstrate 600, an insulator 612 over the conductor 604, an insulator 606a over the insulator 612, a semiconductor 606 b over the insulator 606a, an insulator 606 c over the semiconductor 606 b, a conductor 616 aand a conductor 616 b which are in contact with the insulator 606 a, thesemiconductor 606 b, and the insulator 606 c and which are arranged tobe apart from each other, and an insulator 618 over the insulator 606 c,the conductor 616 a, and the conductor 616 b. The conductor 604 faces abottom surface of the semiconductor 606 b with the insulator 612provided therebetween. The insulator 612 may have a projection. Aninsulator may be provided between the substrate 600 and the conductor604. For the insulator, the description of the insulator 402 or theinsulator 408 is referred to. The insulator 606 a and/or the insulator618 is not necessarily provided.

The semiconductor 606 b serves as a channel formation region of thetransistor. The conductor 604 serves as a first gate electrode (alsoreferred to as a front gate electrode) of the transistor. The conductor616 a and the conductor 616 b serve as a source electrode and a drainelectrode of the transistor.

Note that the insulator 606 a or the insulator 606 c is categorized as asemiconductor in some cases depending on which of the materialsdescribed later is used and the ratio between the materials. Since thesemiconductor 606 b serves as a channel formation region of thetransistor as described above, carriers do not move in the insulator 606a and the insulator 606 c in some cases. Thus, even when the insulator606 a or the insulator 606 c has semiconductor properties, it isreferred to as an insulator in this embodiment.

The insulator 618 is preferably an insulator containing excess oxygen.

For the substrate 600, the description of the substrate 400 is referredto. For the conductor 604, the description of the conductor 404 isreferred to. For the insulator 612, the description of the insulator 412is referred to. For the insulator 606 a, the description of theinsulator 406 c is referred to. For the semiconductor 606 b, thedescription of the semiconductor 406 b is referred to. For the insulator606 c, the description of the insulator 406 a is referred to. For theconductor 616 a and the conductor 616 b, the description of theconductor 416 a and the conductor 416 b is referred to. For theinsulator 618, the description of the insulator 402 is referred to.

Over the insulator 618, a display element may be provided. For example,a pixel electrode, a liquid crystal layer, a common electrode, alight-emitting layer, an organic EL layer, an anode electrode, a cathodeelectrode, or the like may be provided. The display element is connectedto the conductor 616 a or the like, for example.

FIG. 17A is an example of a top view of a transistor. FIG. 17B is anexample of a cross-sectional view taken along dashed-dotted line K1-K2and dashed-dotted line K3-K4 in FIG. 17A. Note that some components suchas an insulator are omitted in FIG. 17A for easy understanding.

Over the insulator 606 c, an insulator that can function as a channelprotective film may be provided. For example, as illustrated in FIGS.17A and 17B, an insulator 620 may be provided between the insulator 606c and the conductors 616 a and 616 b. In that case, the conductor 616 a(conductor 616 b) and the insulator 606 c are connected to each otherthrough an opening in the insulator 620. For the insulator 620, thedescription of the insulator 618 may be referred to.

In FIG. 16B and FIG. 17B, a conductor 613 may be provided over theinsulator 618. Examples in that case are shown in FIGS. 18A and 18B. Forthe conductor 613, the description of the conductor 413 is referred to.A potential or signal which is the same as that supplied to theconductor 604 or a potential or signal which is different from thatsupplied to the conductor 604 may be supplied to the conductor 613. Forexample, by supplying a constant potential to the conductor 613, thethreshold voltage of a transistor may be controlled. In other words, theconductor 613 can function as a second gate electrode. Furthermore, ans-channel structure may be formed using the conductor 613 and the like.

Embodiment 4

An example of the structure of a semiconductor device using thesemiconductor device (cell) according to one embodiment of the presentinvention is described using FIG. 23.

A semiconductor device 1300 shown in FIG. 23 includes a CPU core 1301, apower management unit 1321, and a peripheral circuit 1322. The powermanagement unit 1321 includes a power controller 1302 and a power switch1303. The peripheral circuit 1322 includes a cache 1304 including cachememory, a bus interface (BUS I/F) 1305, and a debug interface (DebugI/F) 1306. The CPU core 1301 includes a data bus 1323, a control unit1307, a PC (program counter) 1308, a pipeline register 1309, a pipelineregister 1310, an ALU (Arithmetic logic unit) 1311, and a register file1312. Data is transmitted between the CPU core 1301 and the peripheralcircuit 1322 such as the cache 1304 via the data bus 1323.

The semiconductor device (cell) according to one embodiment of thepresent invention can be used for many logic circuits typified by thepower controller 1302 and the control unit 1307, particularly to alllogic circuits that can be constituted using standard cells.Accordingly, the semiconductor device 1300 can be small. Thesemiconductor device 1300 can have reduced power consumption. Thesemiconductor device 1300 can have a higher operating speed. Thesemiconductor device 1300 can have a smaller power supply voltagevariation.

When p-channel Si transistors and the transistor described in the aboveembodiment which includes an oxide semiconductor (preferably an oxidecontaining In, Ga, and Zn) in a channel formation region are used in thesemiconductor device (cell) according to one embodiment of the presentinvention and the semiconductor device is used in the semiconductordevice 1300, the semiconductor device 1300 can be small. Thesemiconductor device 1300 can have reduced power consumption. Thesemiconductor device 1300 can have a higher operating speed.Particularly when the Si transistors are only p-channel ones, themanufacturing cost can be reduced.

The control unit 1307 has functions of totally controlling operations ofthe PC 1308, the pipeline register 1309, the pipeline register 1310, theALU 1311, the register file 1312, the cache 1304, the bus interface1305, the debug interface 1306, and the power controller 1302 to decodeand execute instructions contained in a program such as inputapplications.

The ALU 1311 has a function of performing a variety of arithmeticoperations such as four arithmetic operations and logic operations.

The cache 1304 has a function of temporarily storing frequently-useddata. The PC 1308 is a register having a function of storing an addressof an instruction to be executed next. Note that although not shown inFIG. 23, the cache 1304 is provided with a cache controller forcontrolling the operation of the cache memory.

The pipeline register 1309 has a function of temporarily storinginstruction data.

The register file 1312 includes a plurality of registers including ageneral purpose register and can store data that is read from the mainmemory, data obtained as a result of arithmetic operations in the ALU1311, or the like.

The pipeline register 1310 has a function of temporarily storing dataused for arithmetic operations of the ALU 1311, data obtained as aresult of arithmetic operations of the ALU 1311, or the like.

The bus interface 1305 has a function as a path for data between thesemiconductor device 1300 and various devices outside the semiconductordevice 1300. The debug interface 1306 has a function as a path of asignal for inputting an instruction to control debugging to thesemiconductor device 1300.

The power switch 1303 has a function of controlling supply of a powersource voltage to various circuits included in the semiconductor device1300 other than the power controller 1302. The above various circuitsbelong to several different power domains. The power switch 1303controls whether the power supply voltage is supplied to the variouscircuits in the same power domain. In addition, the power controller1302 has a function of controlling the operation of the power switch1303.

The semiconductor device 1300 having the above structure is capable ofperforming power gating. A description will be given of an example ofthe power gating operation sequence.

First, by the CPU core 1301, timing for stopping the supply of the powersupply voltage is set in a register of the power controller 1302. Then,an instruction of starting power gating is sent from the CPU core 1301to the power controller 1302. Then, various registers and the cache 1304included in the semiconductor device 1300 start data storing. Then, thepower switch 1303 stops the supply of a power supply voltage to thevarious circuits other than the power controller 1302 included in thesemiconductor device 1300. Then, an interrupt signal is input to thepower controller 1302, whereby the supply of the power supply voltage tothe various circuits included in the semiconductor device 1300 isstarted. Note that a counter may be provided in the power controller1302 to be used to determine the timing of starting the supply of thepower supply voltage regardless of input of an interrupt signal. Next,the various registers and the cache 1304 start data recovery. Then, theinstruction is resumed in the control unit 1307.

Such power gating can be performed in the whole processor or one or aplurality of logic circuits forming the processor. Furthermore, powersupply can be stopped even for a short time. Consequently, powerconsumption can be reduced finely in terms of a space or time.

In performing power gating, data held by the CPU core 1301 or theperipheral circuit 1322 is preferably restored in a short time. In thatcase, the power can be turned on or off in a short time, and an effectof saving power becomes significant.

In order that the data held by the CPU core 1301 or the peripheralcircuit 1322 be restored in a short time, the data is preferablyrestored to a flip-flop circuit itself (referred to as a flip-flopcircuit capable of backup operation). Furthermore, the data ispreferably restored to an SRAM cell itself (referred to as an SRAM cellcapable of backup operation). The flip-flop circuit and SRAM cell whichare capable of backup operation preferably include transistors includingan oxide semiconductor (preferably an oxide containing In, Ga, and Zn)in a channel formation region. Consequently, the transistor has a lowoff-state current; thus, the flip-flop circuit and SRAM cell which arecapable of backup operation can retain data for a long time withoutpower supply. When the transistor has a high switching speed, theflip-flop circuit and SRAM cell which are capable of backup operationdata can restore and return data in a short time in some cases.

Examples of the flip-flop circuit capable of backup operation and theSRAM cell capable of backup operation are described using FIG. 24 andFIG. 25.

A semiconductor device 1200 shown in FIG. 24 is an example of theflip-flop circuit capable of backup operation. The semiconductor device1200 includes a first memory circuit 1201, a second memory circuit 1202,a third memory circuit 1203, and a read circuit 1204. As a power supplyvoltage, a potential difference between a potential V1 and a potentialV2 is supplied to the semiconductor device 1200. One of the potential V1and the potential V2 is at a high level, and the other is at a lowlevel. An example of the structure of the semiconductor device 1200 whenthe potential V1 is at a low level and the potential V2 is at a highlevel will be described below.

The first memory circuit 1201 has a function of retaining data when asignal D including the data is input in a period during which the powersupply voltage is supplied to the semiconductor device 1200.Furthermore, the first memory circuit 1201 outputs a signal Q includingthe retained data in the period during which the power supply voltage issupplied to the semiconductor device 1200. On the other hand, the firstmemory circuit 1201 cannot retain data in a period during which thepower supply voltage is not supplied to the semiconductor device 1200.That is, the first memory circuit 1201 can be referred to as a volatilememory circuit.

The second memory circuit 1202 has a function of reading the data heldin the first memory circuit 1201 to store (or restore) it. The thirdmemory circuit 1203 has a function of reading the data held in thesecond memory circuit 1202 to store (or restore) it. The read circuit1204 has a function of reading the data held in the second memorycircuit 1202 or the third memory circuit 1203 to store (or return) it in(to) the first memory circuit 1201.

In particular, the third memory circuit 1203 has a function of readingthe data held in the second memory circuit 1202 to store (or restore) iteven in the period during which the power supply voltage is not suppliedto the semiconductor device 1200.

As shown in FIG. 24, the second memory circuit 1202 includes atransistor 1212 and a capacitor 1219. The third memory circuit 1203includes a transistor 1213, a transistor 1215, and a capacitor 1220. Theread circuit 1204 includes a transistor 1210, a transistor 1218, atransistor 1209, and a transistor 1217.

The transistor 1212 has a function of charging and discharging thecapacitor 1219 in accordance with data held in the first memory circuit1201. The transistor 1212 is desirably capable of charging anddischarging the capacitor 1219 at a high speed in accordance with dataheld in the first memory circuit 1201. Specifically, the transistor 1212desirably contains crystalline silicon (preferably polycrystallinesilicon, more preferably single crystal silicon) in a channel formationregion.

The conduction state or the non-conduction state of the transistor 1213is determined in accordance with the charge held in the capacitor 1219.The transistor 1215 has a function of charging and discharging thecapacitor 1220 in accordance with the potential of a wiring 1244 whenthe transistor 1213 is in a conduction state. It is desirable that theoff-state current of the transistor 1215 be extremely low. Specifically,the transistor 1215 desirably contains an oxide semiconductor(preferably an oxide containing In, Ga, and Zn) in a channel formationregion.

Specific connection relations between the elements will be described.One of a source electrode and a drain electrode of the transistor 1212is connected to the first memory circuit 1201. The other of the sourceelectrode and the drain electrode of the transistor 1212 is connected toone electrode of the capacitor 1219, a gate electrode of the transistor1213, and a gate electrode of the transistor 1218. The other electrodeof the capacitor 1219 is connected to the wiring 1242. One of a sourceelectrode and a drain electrode of the transistor 1213 is connected tothe wiring 1244. The other of the source electrode and the drainelectrode of the transistor 1213 is connected to one of a sourceelectrode and a drain electrode of the transistor 1215. The other of thesource electrode and the drain electrode of the transistor 1215 isconnected to one electrode of the capacitor 1220 and a gate electrode ofthe transistor 1210. The other electrode of the capacitor 1220 isconnected to the wiring 1243. One of a source electrode and a drainelectrode of the transistor 1210 is connected to a wiring 1241. Theother of the source electrode and the drain electrode of the transistor1210 is connected to one of a source electrode and a drain electrode ofthe transistor 1218. The other of the source electrode and the drainelectrode of the transistor 1218 is connected to one of a sourceelectrode and a drain electrode of the transistor 1209. The other of thesource electrode and the drain electrode of the transistor 1209 isconnected to one of a source electrode and a drain electrode of thetransistor 1217 and the first memory circuit 1201. The other of thesource electrode and the drain electrode of the transistor 1217 isconnected to a wiring 1240. Furthermore, although a gate electrode ofthe transistor 1209 is connected to a gate electrode of the transistor1217 in FIG. 24, the gate electrode of the transistor 1209 is notnecessarily connected to the gate electrode of the transistor 1217.

The transistor described in the above embodiment as an example can beapplied to the transistor 1215. Because of the low off-state current ofthe transistor 1215, the semiconductor device 1200 can retain data for along time without power supply. The favorable switching characteristicsof the transistor 1215 allow the semiconductor device 1200 to performhigh-speed backup and recovery.

The semiconductor device 1100 shown in FIG. 25 is an example of the SRAMcell capable of backup operation. The semiconductor device 1100 includestransistors (M101, M102, Mos1, and Mos2), inverters (INV101 and INV102),and capacitors (C101 and C102). The semiconductor device 1100 isconnected to wirings (WL, BL, BLB, and BRL). In addition, the low powersupply voltage (VSS) and the like are supplied as power supply voltagesto the semiconductor device 1100.

An input node and an output node of the inverter INV101 are connectedwith an output node and an input node of the inverter INV102,respectively, whereby an inverter loop circuit is formed. A gateelectrode of the transistor M101 and a gate electrode of the transistorM102 are connected to the wiring WL. The transistor M101 functions as aswitch connecting the wiring BL and the input node of the inverterINV101, and the transistor M102 functions as a switch connecting thewiring BLB and the input node of the inverter INV102.

The wiring WL functions as a writing/reading word line, and a signal(WLE) for selecting a memory cell is input from a word line drivercircuit. The wirings BL and BLB function as bit lines that send signalsD and DB. The signal DB is a signal that is obtained by inverting thelogic value of the signal D. The signals D and DB are supplied from abit line driver circuit. Furthermore, the wirings BL and BLB are alsowirings for transmitting data read from the semiconductor device 1100 toan output circuit.

The semiconductor device 1100 corresponds to a circuit including avolatile memory circuit (INV101, INV102, M101, and M102) and a pair ofmemory circuits (Mos1 and C101) and (Mos2 and C102). The memory circuits(Mos1 and C101) and (Mos2 and C102) are each a circuit for backing updata of the volatile memory circuit by storing potentials held in a nodeNET1 and a node NET2, respectively. These memory circuits turn on thetransistors Mos1 and Mos2 to charge or discharge the capacitors C101 andC102 so that data is written, and turns off them to store chargeaccumulated in the capacitors so that data is retained without powersupply.

Data is recovered by turning on the transistors Mos1 and Mos2. Thetransistors Mos1 and Mos2 are turned on while power supply to theinverters INV101 and INV102 is stopped, whereby a node FN1 and a nodeNET1 are connected so that charge is shared by the node FN1 and the nodeNET1, and a node FN2 and a node NET2 are connected so that charge isshared by the node FN2 and the node NET2. Then, power is supplied to theinverters INV101 and INV102, whereby data is returned to an inverterloop circuit, depending on the potentials of the node NET1 and the nodeNET2. After that, the transistors Mos1 and Mos2 are turned off.

Gate electrodes of the transistors Mos1 and Mos2 are connected to thewiring BRL. A signal OSG is input to the wiring BRL. In response to thesignal OSG, the pair of memory circuits (Mos1, C101) and (Mos2, C102))is driven and backup or recovery is performed.

Configurations and operations of the memory circuit (Mos1, C101) and thememory circuit (Mos2, C102) are described below.

The memory circuits (Mos1 and C101) and (Mos2 and C102) store charge inthe capacitors C101 and C102, thereby holding the potentials of thenodes FN1 and FN2. When the transistors Mos1 and Mos2 are turned on, thenode NET1 and the node FN1 are connected and the potential held in thenode NET1 is applied to the node FN1. Furthermore, when the transistorMos2 is turned on, the node NET2 and the node FN2 are connected and thepotential held in the node NET2 is applied to the node FN2. In addition,turning off the transistors Mos1 and Mos2 brings the nodes FN1 and FN2into an electrically floating state, so that charge stored in thecapacitors C101 and C102 is held and the memory circuits are broughtinto a data holding state.

For example, in the case where the node FN1 is at H level, charge mayleak from C101, gradually decreasing the voltage thereof. Thetransistors Mos1 and Mos2 desirably contain an oxide semiconductor(preferably an oxide containing In, Ga, and Zn) in a channel formationregion. Consequently, the leakage current flowing between a sourceelectrode and a drain electrode in an off state (off-state current) isextremely low; thus, a voltage variation of the node FN1 can besuppressed. That is to say, the circuit including the transistor Mos1and the capacitor C101 can be operated as a nonvolatile memory circuitor a memory circuit that can retain data for a long time without powersupply. Furthermore, in a similar manner, the circuit including thetransistor Mos2 and the capacitor C102 can be used as a backup memorycircuit of the volatile memory circuit (INV101, INV102, M101, and M102).

The transistor described as an example in the above embodiment can beused as the transistors Mos1 and Mos2. Because of the low off-statecurrent of the transistors Mos1 and Mos2, the semiconductor device 1100can retain data for a long time without power supply. The favorableswitching speed of the transistors Mos1 and Mos2 allows thesemiconductor device 1100 to perform high-speed backup and recovery.

The semiconductor device (cell) according to one embodiment of thepresent invention, and the flip-flop circuit and SRAM cell, which arecapable of backup operation and use the transistor which includes anoxide semiconductor in a channel formation region and is described as anexample in the above embodiment, can be used in the semiconductor device1300, so that the power of the semiconductor device can be turned on oroff in a short time and power consumption thereof can further bereduced.

The transistor described as an example in the above embodiment can beused in the semiconductor device (cell) according to one embodiment ofthe present invention or the flip-flop circuit and SRAM cell, which arecapable of backup operation and includes the oxide semiconductor in achannel formation region in the semiconductor device 1300 to reduce themanufacturing cost thereof. In particular, n-channel transistors used inthe flip-flop circuit and the SRAM cells may each be replaced with thetransistor which includes an oxide semiconductor in a channel formationregion and is described as an example in the above embodiment. When Sitransistors are only p-channel ones, manufacturing cost can be reduced.

The semiconductor device (cell) according to one embodiment of thepresent invention can be used for a graphics processing unit (GPU), aprogrammable logic device (PLD), a digital signal processor (DSP), amicrocontroller unit (MCU), a radio frequency integrated circuit (RFIC),a custom LSI, and the like as well as a CPU.

Embodiment 5

In this embodiment, application examples of the semiconductor device(cell) according to one embodiment of the present invention aredescribed.

FIG. 26A shows a perspective view illustrating a part of the inside of apackage including a lead frame type interposer. In the packageillustrated in FIG. 26A, a chip 1751 to which the semiconductor device(cell) according to one embodiment of the present invention is appliedis connected to a terminal 1752 over an interposer 1750 by a wirebonding method. The terminal 1752 is placed on a surface of theinterposer 1750 on which the chip 1751 is mounted. In addition, the chip1751 may be sealed by a mold resin 1753, in which case it is sealed sothat part of each of the terminals 1752 is exposed.

FIG. 26B illustrates the structure of a module of an electronic device(mobile phone) in which a package is mounted on a circuit board. In themodule of a mobile phone shown in FIG. 26B, a package 1762 and a battery1764 are mounted on a printed circuit board 1761. In addition, theprinted circuit board 1761 is mounted on a panel 1760 provided withdisplay elements by an FPC 1763.

Embodiment 6

An example of the structure of a semiconductor device including thesemiconductor device (cell) according to one embodiment of the presentinvention is described using FIG. 28, FIG. 29, FIG. 30, and FIG. 31.

FIG. 28 shows an example of a structure of a semiconductor device. Asemiconductor device 1600 shown in FIG. 28 is an example of asemiconductor device that can function as a memory device. Thesemiconductor device 1600 includes a memory cell array 1610, a rowdecoder 1621, a word line driver circuit 1622, a bit line driver circuit1630, an output circuit 1640, and a control logic circuit 1660.

The bit line driver circuit 1630 includes a column decoder 1631, aprecharge circuit 1632, a sense amplifier 1633, and a writing circuit1634. The precharge circuit 1632 has a function of precharging wirings(BL and BLB) and a function of making the voltages of the wiring BL andthe wiring BLB in the same column equal. The sense amplifier 1633 has afunction of amplifying signals (D and DB) read from the wirings (BL andBLB). The amplified signals are output to the outside of thesemiconductor device 1600 as digital signals RDATA, through the outputcircuit 1640.

Furthermore, to the semiconductor device 1600, a low power supplyvoltage (VSS), a high power supply voltage (VDD) for a circuit portion1601 other than the memory cell array, and a high power supply voltage(VIL) for the memory cell array 1610 are supplied from the outside aspower supply voltages.

In addition, to the semiconductor device 1600, control signals (CE, WE,and RE), an address signal ADDR, and a signal WDATA are input from theoutside. ADDR is input to the row decoder 1621 and the column decoder1631, and WDATA is input to the writing circuit 1634.

The control logic circuit 1660 processes the signals (a signal CE, asignal WE, and a signal RE) input from the outside, and generatessignals for the row decoder 1621 and the column decoder 1631. The signalCE is a chip enable signal, the signal WE is a write enable signal, andthe signal RE is a read enable signal. Signals processed by the controllogic circuit 1660 are not limited thereto, and other signals may beinput as necessary.

Note that whether each circuit or each signal described above isprovided or not can be determined as appropriate as needed.

The semiconductor device (cell) according to one embodiment of thepresent invention can be used for the row decoder 1621, the word linedriver circuit 1622, the bit line driver circuit 1630, the outputcircuit 1640, and the control logic circuit 1660, particularly to allthe logic circuits that can be formed using a standard cell.Accordingly, the semiconductor device 1600 can be small. Thesemiconductor device 1600 can have reduced power consumption. Thesemiconductor device 1600 can have a higher operating speed.

When p-channel Si transistors and the transistor described in the aboveembodiment which includes an oxide semiconductor (preferably an oxidecontaining In, Ga, and Zn) in a channel formation region are used in thesemiconductor device (cell) according to one embodiment of the presentinvention and the semiconductor device is used in the semiconductordevice 1600, the semiconductor device 1600 can be small. Thesemiconductor device 1600 can have reduced power consumption. Thesemiconductor device 1600 can have a higher operating speed.Particularly when the Si transistors are only p-channel ones, themanufacturing cost can be reduced.

Note that a transistor including an oxide semiconductor (preferably anoxide containing In, Ga, and Zn) in a channel formation region can beused in the memory cell array 1610. An example of such a memory cellwill be described below using FIG. 29, FIG. 30, and FIG. 31.

FIG. 29 is a circuit diagram showing a configuration example of a memorycell. A memory cell 1103 includes a transistor Mos3 and a capacitorC103. A node FN3 is a data holding portion, and a terminal of thecapacitor C103 is connected thereto. The transistor Mos3 functions as aswitch connecting the node FN3 and the wiring BL, and a gate electrodethereof is connected to the wiring WL. As a signal for selecting amemory cell, the signal OSG is input to the wiring WL.

FIG. 30 is a circuit diagram showing a configuration example of a memorycell. A memory cell 1104 includes a transistor Mos4, a transistor M104,and a capacitor C104. Anode FN4 is a data holding portion. Thetransistor Mos4 functions as a switch connecting the node FN4 and awiring BL, and a gate electrode thereof is connected to the wiring WL.The signal OSG is input to the wiring WL. The capacitor C104 connects awiring WLC and the node FN4. The wiring WLC is a wiring for supplying aconstant voltage to a terminal of C104 at the time of a writingoperation and at the time of a reading operation. The transistor M104 isa p-channel transistor, and a gate electrode, a source electrode, and adrain electrode thereof are connected to the node FN4, a wiring SL, andthe wiring BL, respectively.

While a constant voltage is applied to the wirings WLC and SL, data iswritten by turning on the transistor Mos4 and connecting the node FN4 tothe wiring BL. For reading data, a constant voltage is applied to thewirings BL, WLC, and SL. The value of a current flowing between a sourceelectrode and a drain electrode of the transistor M104 changes dependingon the voltage of the node FN4. The wiring BL is charged or dischargedby the source electrode-drain electrode current of the transistor M104,so that the data value held in the memory cell 1104 can be read bydetecting the voltage of the wiring BL.

Note that the transistor M104 can be an n-channel transistor. Inaccordance with the conductivity type of the transistor M104, a voltageapplied to the wirings BL, SL, and WLC is determined.

FIG. 31 is a circuit diagram showing a configuration example of a memorycell. A memory cell 1105 includes a transistor Mos5, a transistor M105,a transistor M106, and a capacitor C105. A node FN5 is a data holdingportion. The transistor Mos5 functions as a switch connecting the nodeFN5 and the wiring BL, and a gate electrode thereof is connected to thewiring WL. The signal OSG is input to the wiring WL. The transistorsM105 and M106 connect the wiring BL and one terminal of the capacitorC105. A gate electrode of the transistor M105 is connected to a wiringRWL, and a gate electrode of the transistor M106 is connected to thenode FN5. In addition, the other terminal of the capacitor C105 isconnected to the node FN5.

Data is written by turning on the transistor Mos5 and connecting thenode FN4 to the wiring BL. Data is read by turning on the transistorM105. The value of a current flowing between a source electrode and adrain electrode of the transistor M106 changes depending on the voltageof the node FN5. The wiring BL is charged or discharged by the sourceelectrode-drain electrode current of the transistor M106, so that thedata value held in the memory cell 1105 can be read by detecting thevoltage of the wiring BL.

Note that the transistors M105 and M106 can be p-channel transistors. Inaccordance with the conductivity type of the transistors M105 and M106,a voltage applied to the wiring RWL and a voltage applied to thecapacitor C105 should be determined.

In the configuration examples of the memory cells shown in FIG. 29 toFIG. 31, the transistors Mos3, Mos4, and Mos5 desirably include oxidesemiconductors (preferably, oxides containing In, Ga, and Zn) in channelformation regions. As a result, since a leakage current (off-statecurrent) that flows between a source electrode and a drain electrode ofthe transistor in an off-state is extremely low, a fluctuation in thevoltage of the nodes FN3, FN4, and FN5 can be suppressed. That is tosay, a circuit including the transistor Mos3 and the capacitor C103, acircuit including the transistor Mos4 and the capacitor C104, and acircuit including the transistor Mos3 and the capacitor C103 can each beoperated as a nonvolatile memory circuit or a memory circuits capable ofholding data for a long time without power supply.

The semiconductor device (cell) according to one embodiment of thepresent invention and the memory cell using the transistor whichincludes an oxide semiconductor in a channel formation region and isdescribed as an example in the above embodiment can be used in thesemiconductor device 1600, so that the semiconductor device thatincludes a nonvolatile memory circuit or a memory circuit capable ofholding data for a long time without power supply can have a smallersize, reduced power consumption, a higher operating speed, or a smallerpower supply voltage variation.

The transistor described as an example in the above embodiment can beused in the semiconductor device (cell) according to one embodiment ofthe present invention or the memory cell using a transistor includingthe oxide semiconductor in a channel formation region in thesemiconductor device 1600 to reduce the manufacturing cost thereof. Inparticular, re-channel transistors used in the memory cell may each bereplaced with the transistor which includes an oxide semiconductor in achannel formation region and is described as an example in the aboveembodiment in channel formation regions. When Si transistors are onlyp-channel ones, manufacturing cost can be reduced.

Note that this embodiment can be combined as appropriate with the otherembodiments described in this specification.

Embodiment 7

An example of the structure of a device using the semiconductor device(cell) according to one embodiment of the present invention is describedusing FIG. 27.

A semiconductor device 1800 shown in FIG. 27 is an example of thestructure of an RFIC. An RFIC in this embodiment includes a memorycircuit inside, stores necessary data in the memory circuit, andtransmits and receives data to/from the outside by using contactlessmeans, for example, wireless communication. With such characteristics,an RFIC can be used for an individual authentication system in which anobject is recognized by reading the individual information of the objector the like, for example. An RFIC may be referred to as an RF chip, anRF tag, an RFID, or the like.

The semiconductor device 1800 shown in FIG. 27 includes an antenna 1804,a rectifier circuit 1805, a constant voltage circuit 1806, ademodulation circuit 1807, a modulation circuit 1808, a logic circuit1809, a memory circuit 1810, and a ROM 1811.

The antenna 1804 is a circuit for sending and receiving a radio signal1803 with the antenna 1802 connected to a communication device 1801. Inaddition, the rectifier circuit 1805 is a circuit for generating aninput potential by rectification, for example, half-wave voltage doublerrectification of the input alternating signal generated by reception ofa radio signal at the antenna 1804 and smoothing of the rectified signalwith a capacitor provided in a later stage. Note that a limiter circuitmay be provided on the input side or the output side of the rectifiercircuit 1805. The limiter circuit is a circuit for controlling electricpower so that electric power that is higher than or equal to certainelectric power is not input to a circuit in a later stage in the casewhere the amplitude of the input alternating signal is high and aninternal generation voltage is high.

The constant voltage circuit 1806 is a circuit for generating a stablepower supply voltage from an input potential and supplying it to eachcircuit. Note that the constant voltage circuit 1806 may include a resetsignal generation circuit. The reset signal generation circuit generatesa reset signal of the logic circuit 1809 by utilizing the rise of thestable power supply voltage.

The demodulation circuit 1807 is a circuit for demodulating the inputalternating signal by envelope detection and generating the demodulatedsignal. Furthermore, the modulation circuit 1808 performs modulation inaccordance with data to be output from the antenna 1804.

The logic circuit 1809 is a circuit for decoding and processing thedemodulated signal. The memory circuit 1810 holds the input data andincludes a row decoder, a column decoder, a memory region, and the like.Furthermore, the ROM 1811 stores an identification number (ID) or thelike and outputs it in accordance with processing.

Note that data transmission formats include an electromagnetic couplingmethod in which a pair of coils is provided so as to face each other andcommunicates with each other by mutual induction, an electromagneticinduction method in which communication is performed using an inductionfield, a radio wave method in which communication is performed using aradio wave, and the like. The semiconductor device 1800 described inthis embodiment can be used for any of the methods.

Note that whether each circuit described above is provided or not can bedetermined as appropriate as needed.

The semiconductor device (cell) according to one embodiment of thepresent invention can be used for the logic circuit 1809, the memorycircuit 1810, the ROM 1811, and the like, particularly to all logiccircuits that can be constituted using standard cells. Accordingly, thesemiconductor device 1800 can be small. The semiconductor device 1800can have reduced power consumption. The semiconductor device 1800 canhave a higher operating speed.

When p-channel Si transistors and the transistor described in the aboveembodiment which includes an oxide semiconductor (preferably an oxidecontaining In, Ga, and Zn) in a channel formation region are used in thesemiconductor device (cell) according to one embodiment of the presentinvention and the semiconductor device is used in the semiconductordevice 1800, the semiconductor device 1800 can be small. Thesemiconductor device 1800 can have reduced power consumption. Thesemiconductor device 1800 can have a higher operating speed.Particularly when the Si transistors are only p-channel ones, themanufacturing cost can be reduced.

Note that the memory circuit described in the above embodiment can beused as the memory circuit 1810. Furthermore, the transistor describedin the above embodiment which includes an oxide semiconductor(preferably an oxide containing In, Ga, and Zn) in a channel formationregion may be used as an element having a rectifying function includedin the demodulation circuit 1807. Since the transistor has a lowoff-state current, the reverse current of the element having arectifying function can be reduced. Consequently, excellentrectification efficiency can be achieved.

Note that this embodiment is not limited to the above-describedstructure. For example, a battery not shown in FIG. 27 may beincorporated so as to form an active-type RFIC.

Note that this embodiment can be combined as appropriate with the otherembodiments described in this specification.

Embodiment 8

An example of the structure of a semiconductor device (imaging device)according to one embodiment of the present invention is described withreference to FIGS. 33A and 33B and FIG. 34.

FIG. 33A is a top view of the imaging device of one embodiment of thepresent invention and shows an example of a specific connection betweena photoelectric conversion element 60, a transistor 51, a transistor 52,a transistor 53, and a transistor 54 which are included in a pixelcircuit illustrated in FIG. 34. FIG. 33B is a cross-sectional view alongthe dash-dot line A5-A6 in FIG. 33A. Note that in the above drawings,some components are not illustrated for clarity.

The electrical connection between the above components is only anexample. Although the wirings, the electrodes, and a conductor 81 areillustrated as independent components in the drawings, some of them areprovided as one component in some cases when they are electricallyconnected to each other. In addition, an insulator 41 and an insulator42 that serve as interlayer insulating films or planarizing films areprovided between the components.

For example, an inorganic insulating film such as a silicon oxide filmor a silicon oxynitride film can be used as the insulators 41 and 42.Alternatively, an organic insulating film such as an acrylic resin filmor a polyimide resin film may be used. The top surfaces of theinsulators 41 and 42 are preferably planarized by a chemical mechanicalpolishing (CMP) method or the like.

In some cases, one or more of the wirings are not provided or anotherwiring or transistor is included in each layer. Furthermore, anotherlayer may be included in the stacked-layer structure. One or more of thelayers are not included in some cases.

In the pixel circuit, one of a source electrode and a drain electrode ofa transistor 51 is electrically connected to one electrode 66 of aphotoelectric conversion element 60. The other of the source electrodeand the drain electrode of the transistor 51 is electrically connectedto a gate electrode of a transistor 52. The other of the sourceelectrode and the drain electrode of the transistor 51 is alsoelectrically connected to one of a source electrode and a drainelectrode of a transistor 53. One of a source electrode and a drainelectrode of the transistor 52 is electrically connected to one of asource electrode and a drain electrode of a transistor 54. Although notillustrated in FIGS. 33A and 33B, the other of the source electrode andthe drain electrode of the transistor 51 may be electrically connectedto one electrode of a capacitor 58 as illustrated in FIG. 34.

The source electrode and the drain electrode of each transistor canfunction as wirings. For example, one of wirings 71 and 79 can functionas a power supply line, and the other of the wirings 71 and 79 canfunction as an output line. A wiring 72 can function as a power supplyline. A wiring 77 can function as a power supply line (low-potentialpower supply line). Wirings 75, 76, and 78 can function as signal linesfor controlling the on/off states of transistors. A wiring 74 canfunction as a connection wiring.

Here, the transistor 51 can function as a transfer transistor forcontrolling the potential of a charge accumulation portion (FD) inresponse to output of the photoelectric conversion element 60. Thetransistor 52 can function as an amplifying transistor that outputs asignal based on the potential of the charge accumulation portion (FD).The transistor 53 can function as a reset transistor for initializingthe potential of the charge accumulation portion (FD). The transistor 54can function as a selection transistor for selecting a pixel.

A transistor including an oxide semiconductor in an active layer(hereinafter also referred to as an OS transistor) can be used as thetransistors 51 to 54.

Extremely low off-state current characteristics of the OS transistor canwiden the dynamic range of image-capturing. In the circuit shown in FIG.34, an increase in the intensity of light entering the photoelectricconversion element 60 reduces the potential of the charge storageportion (FD). Since the transistor using an oxide semiconductor has anextremely low off-state current, a current corresponding to the gatepotential can be accurately output even when the gate potential isextremely low. Thus, it is possible to widen the detection range ofilluminance, i.e., the dynamic range.

A period during which charge can be retained in the charge storageportion (FD) can be extremely long owing to the low off-state currentcharacteristics of the transistors 51 and 53. Therefore, a globalshutter system, in which charge accumulation operation is performed inall the pixel circuits at the same time, can be used without acomplicated circuit configuration and operation method, and thus, animage with little distortion can be easily obtained even in the case ofa moving object. Furthermore, exposure time (a period for conductingcharge accumulation operation) can be long in a global shutter system;thus, the imaging device is suitable for imaging even in a lowilluminance environment.

In addition, the OS transistor has lower temperature dependence ofchange in electrical characteristics than the Si transistor, and thuscan be used in an extremely wide range of temperatures. Therefore, animaging device and a semiconductor device which include OS transistorsare suitable for use in automobiles, aircrafts, and spacecrafts.

Furthermore, the OS transistor has higher drain breakdown voltage thanthe Si transistor. In a photoelectric conversion element including aselenium-based material in a photoelectric conversion layer, arelatively high voltage (e.g., 10 V or more) is preferably applied toeasily cause the avalanche phenomenon. Therefore, by combination of theOS transistor and the photoelectric conversion element including aselenium-based material in the photoelectric conversion layer, a highlyreliable imaging device can be obtained.

This embodiment can be combined with any of the other embodiments inthis specification as appropriate.

Embodiment 9

The semiconductor device (cell) according to one embodiment of thepresent invention can be used for display devices, personal computers,image reproducing devices provided with recording media (typically,devices which reproduce the content of recording media such as digitalversatile discs (DVDs) and have displays for displaying the reproducedimages), or the like. Other examples of electronic devices that can beequipped with the semiconductor device (cell) according to oneembodiment of the present invention are mobile phones, game machinesincluding portable game consoles, portable data appliances, e-bookreaders, cameras such as video cameras and digital still cameras,goggle-type displays (head mounted displays), navigation systems, audioreproducing devices (e.g., car audio systems and digital audio players),copiers, facsimiles, printers, multifunction printers, automated tellermachines (ATM), and vending machines. FIGS. 32A to 32F illustratespecific examples of these electronic devices.

FIG. 32A illustrates a portable game console including a housing 1901, ahousing 1902, a display portion 1903, a display portion 1904, amicrophone 1905, a speaker 1906, an operation key 1907, a stylus 1908,and the like. Although the portable game machine in FIG. 32A has the twodisplay portions 1903 and 1904, the number of display portions includedin a portable game machine is not limited to this.

FIG. 32B illustrates a portable data terminal including a first housing1911, a second housing 1912, a first display portion 1913, a seconddisplay portion 1914, a joint 1915, an operation key 1916, and the like.The first display portion 1913 is provided in the first housing 1911,and the second display portion 1914 is provided in the second housing1912. The first housing 1911 and the second housing 1912 are connectedto each other with the joint 1915, and the angle between the firsthousing 1911 and the second housing 1912 can be changed with the joint1915. An image on the first display portion 1913 may be switcheddepending on the angle between the first housing 1911 and the secondhousing 1912 at the joint 1915. A display device with a position inputfunction may be used as at least one of the first display portion 1913and the second display portion 1914. Note that the position inputfunction can be added by provision of a touch panel in a display device.Alternatively, the position input function can be added by provision ofa photoelectric conversion element called a photosensor in a pixelportion of a display device.

FIG. 32C illustrates a laptop personal computer, which includes ahousing 1921, a display portion 1922, a keyboard 1923, a pointing device1924, and the like.

FIG. 32D illustrates an electric refrigerator-freezer including ahousing 1931, a door for a refrigerator 1932, a door for a freezer 1933,and the like.

FIG. 32E illustrates a video camera including a first housing 1941, asecond housing 1942, a display portion 1943, operation keys 1944, a lens1945, a joint 1946, and the like. The operation keys 1944 and the lens1945 are provided for the first housing 1941, and the display portion1943 is provided for the second housing 1942. The first housing 1941 andthe second housing 1942 are connected to each other with the joint 1946,and the angle between the first housing 1941 and the second housing 1942can be changed with the joint 1946. Images displayed on the displayportion 1943 may be switched in accordance with the angle at the joint1946 between the first housing 1941 and the second housing 1942.

FIG. 32F illustrates an ordinary vehicle including a car body 1951,wheels 1952, a dashboard 1953, lights 1954, and the like.

Example 1

(Oxygen Vacancy)

This example shows device calculations of transistors each including anoxide semiconductor, which were performed to examine an effect of oxygenvacancies inside the oxide semiconductor on the transistors, and theresults of the calculations.

In this example, 2D calculations were performed using the devicesimulator “ATLAS” produced by Silvaco Inc. as calculation software.

A structure of a transistor for the calculations for a bias-temperaturestress test is described. A transistor 300A in FIG. 19 shows thestructure and size of the transistor used in the calculations for thebias-temperature stress test. The transistor 300A includes a substrate301, a conductor 302 serving as a gate electrode over the substrate 301,an insulator 311 over the conductor 302, an oxide semiconductor 303 overthe insulator 311, a conductor 304 and a conductor 305 serving as asource electrode and a drain electrode over the oxide semiconductor 303,and an insulator 306 over the oxide semiconductor 303 and the conductors304 and 305.

The parameters and constants of the transistor 300A used in thecalculations are as follows. The conductor 302 has a work function of 5eV. The insulator 311 has a thickness of 150 nm and a dielectricconstant of 4.1. The oxide semiconductor 303 has a thickness of 45 nm,an electron affinity of 4.6 eV, a 3.2 eV energy barrier between thevalence and conduction bands, a dielectric constant of 15, an electronmobility of 10 cm²/Vs, and a hole mobility of 0.01 cm²/Vs, and theeffective densities of states in the valence and conduction bands areeach 5.00×10¹⁸/cm³. An oxide semiconductor 303 b in contact with theinsulator 306 has a donor density of 6.60×10⁻⁹/cm³. An oxidesemiconductor 303 a and an oxide semiconductor 303 c, which are justunder the conductor 304 and the conductor 305, respectively, each have adonor density of 5.00×10¹⁸/cm³. The conductors 304 and 305 each have awork function of 4.6 eV. The insulator 306 has a dielectric constant of4.1 and a thickness of 400 nm.

FIG. 36A shows the calculation results of an electric field distributionin the oxide semiconductor 303 of the transistor 300A, which wasobtained when potentials of 20 V and 30 V were applied to the conductor302 and the conductor 305, respectively, in the transistor 300A. FIG.36B shows explanatory notes of the strength of the electric field. FIGS.36A and 36B reveal that there is an electric field greater than or equalto 1.0×10⁵ V/cm at the interface between the oxide semiconductor 303 andthe insulator 311 and at a position of the oxide semiconductor 303,which is just under the boundary between the conductor 305 and theinsulator 306. Note that the white color of the conductors 304 and 305and the insulators 306 and 311 in FIG. 36A does not indicate an electricfield inside the conductors 304 and 305 and the insulators 306 and 311;only the strength of the electric field in the oxide semiconductor 303is shown.

FIG. 35 illustrates a transistor 300B including the oxide semiconductor303. The thickness of the oxide semiconductor is 100 nm and is the onlydifference from the transistor 300A.

FIG. 37A shows the calculation results of an electric field in the oxidesemiconductor 303 of the transistor 300B, which was obtained whenpotentials of 20 V and 30 V were applied to the conductor 302 and theconductor 305, respectively, in the transistor 300B. FIG. 37B showsexplanatory notes of the strength of the electric field. FIGS. 37A and37B reveal that there is an electric field greater than or equal to5.62×10⁴ V/cm at the interface between the oxide semiconductor 303 andthe insulator 311 and at a position of the oxide semiconductor 303,which is just under the boundary between the conductor 305 and theinsulator 306. Note that the white color of the conductors 304 and 305and the insulators 306 and 311 in FIG. 37A does not indicate an electricfield inside the conductors 304 and 305 and the insulators 306 and 311;only the strength of the electric field in the oxide semiconductor 303is shown.

FIG. 36A and FIG. 37A show that, despite the thickness of the oxidesemiconductor 303, application of high potentials to the conductors 302and 305 causes generation of local electric fields at the interfacebetween the oxide semiconductor 303 and the insulator 311 and at theposition of the oxide semiconductor 303, which is just under theboundary between the conductor 305 and the insulator 306.

Continuous application of a strong local electric field in an oxidesemiconductor might significantly increase the value of current flowingthrough the oxide semiconductor between the source electrode and thedrain electrode after several hundreds or thousands of seconds, althoughdepending on the constituent elements, structure, or density of theoxide semiconductor. The significant increase in current value may beattributed to oxygen vacancies V_(O) generated by a local electric fieldin the oxide semiconductor.

V_(O) generated in the oxide semiconductor forms DOS and serves as holetraps or the like. In addition, hydrogen included in the oxidesemiconductor or in the source electrode, drain electrode, gateinsulating film, or the like in contact with the oxide semiconductormight enters the sites of such oxygen vacancies V_(O) and forms a donorlevel, increasing the donor density in the oxide semiconductor (hydrogenentering the sites of oxygen vacancies are also referred to as V_(O)H).As a bias-temperature stress test is continued, V_(O) is increased andV_(O)H might also be increased.

Next, the behavior of the transistor with various donor densities isdescribed. FIG. 38 shows the calculation results of current-voltagecharacteristics of the transistor 300A described above. In thecalculations, the oxide semiconductors 303 of samples had differentdonor densities.

The donor densities of a sample I, a sample J, a sample K, a sample L,and a sample M were 6.6×10⁻⁹/cm³, 1.0×10¹⁶/cm³, 1.0×10¹⁷/cm³,1.0×10¹⁸/cm³, and 1.0×10¹⁹/cm³, respectively. FIG. 38 reveals that, asthe donor density is increased, the threshold voltage of the transistor300A is shifted in the negative direction. In particular, when the donordensity is increased to 1.0×10¹⁸/cm³ or more, the threshold voltage isreduced to −10 V or less. The samples L and M were in an on-state at agate-source voltage greater than or equal to −10 V and less than orequal to 10 V.

V_(O)H generated when hydrogen is trapped by V_(O) in an oxidesemiconductor serve as a carrier supply source of an n-type donor in theoxide semiconductor. Therefore, the donor density of the oxidesemiconductor is increased, which might shift the threshold voltage ofthe transistor including the oxide semiconductor in the negativedirection, as shown in the above calculation results (FIG. 38).

As the bias-temperature stress test is further continued, V_(O) isincreased and V_(O)H serving as a carrier supply source of an n-typedonor is increased. Accordingly, the oxide semiconductor might be in anon-state at a gate-source voltage in a wide range, like the sample L andthe sample M, as in FIG. 38.

Note that a generation mechanism of V_(O) is not limited to the above.For example, in a formation process of the transistor 300A, after theconductor 302, the insulator 311, the oxide semiconductor 303, theconductor 304, the conductor 305, and the insulator 306 are formed overthe substrate 301, a high-temperature baking in a nitrogen atmospheremight cause oxygen (an oxygen molecule, an oxygen atom, and an oxygenion are collectively referred to as oxygen in this specification) in theoxide semiconductor 303 to react with hydrogen in the oxidesemiconductor 303 and the insulator 306, the insulator 311, theconductor 304, or the conductor 305 in contact with the oxidesemiconductor 303 to produce a water molecule (also referred to as waterin this specification) or a hydroxide ion. Then, release of the watermolecule or hydroxide ion from the transistor might generate V_(O) inthe oxide semiconductor 303.

The function of a transistor including an oxide semiconductor isdegraded by oxygen vacancies V_(O) in the oxide semiconductor and V_(O)Hformed of hydrogen entering the oxygen vacancies V_(O). To fabricate atransistor having high drain breakdown voltage, a dense oxidesemiconductor that does not allow a bias-temperature stress test togenerate V_(O) and has little V_(O) and little hydrogen are needed to beformed.

Note that generation of an electric field, generation of oxygenvacancies, and current flow between a source and a drain, which arecaused by a bias-temperature stress test as described above, are notnecessarily caused only in the above-described structure of thetransistor 300A and may be caused in a transistor having any structure.

(Method of Manufacturing Dense Oxide Semiconductor)

An example of a method of manufacturing a dense oxide semiconductorCAAC-OS is described below using FIG. 20.

The formation of an oxide semiconductor needs heat treatment after thedeposition of the oxide semiconductor in Embodiment 1. As the heattreatment, a thermal annealing step, a rapid thermal annealing (RTA)step, and the like can be given, and an RTA step with a lamp ispreferably employed to form a denser oxide semiconductor.

In particular, heat treatment with an RTA apparatus in an oxygenatmosphere is preferably performed to reduce oxygen vacancies V_(O) inan oxide semiconductor CAAC-OS. Heat treatment in an oxygen atmospherecan supply oxygen without disordering crystallinity of a CAAC-OS, sothat oxygen can enter the sites of oxygen vacancies V_(O) generated inthe deposition of the CAAC-OS.

FIG. 20 shows the results of the film densities of CAAC-OSs eachincluding an In—Ga—Zn oxide, which were measured by X-ray reflectometry(XRR). A substrate to be provided with the In—Ga—Zn oxide was a siliconsubstrate including a 100-nm-thick thermal oxidation film and a300-nm-thick oxynitride film over the thermal oxidation film. TheIn—Ga—Zn oxide was deposited under the following conditions: asputtering target having an atomic ratio of In:Ga:Zn=1:1:1.2 was used;the distance between the target and the substrate was 60 mm; argon andoxygen were supplied at flow rates of 30 sccm and 15 sccm, respectively;the pressure was 0.7 Pa; and a 0.5 kW DC power source was used.

For a sample B, heat treatment was performed at 450° C. using a furnacein a nitrogen atmosphere for one hour and then performed at 450° C.using the same furnace in an oxygen atmosphere for one hour. For asample C, heat treatment was performed at 500° C. using a furnace in anitrogen atmosphere for one hour and then performed at 500° C. using thesame furnace in an oxygen atmosphere for one hour. For a sample D, heattreatment was performed at 550° C. using a furnace in a nitrogenatmosphere for one hour and then performed at 550° C. using the samefurnace in an oxygen atmosphere for one hour. For a sample E, heattreatment was performed at 700° C. using an RTA apparatus in an oxygenatmosphere for 30 secs. For a sample F, heat treatment was performed at700° C. using an RTA apparatus in an oxygen atmosphere for 60 secs. Fora sample G, heat treatment was performed at 700° C. using an RTAapparatus in an oxygen atmosphere for 120 secs. For a sample H, heattreatment was performed at 700° C. using an RTA apparatus in an oxygenatmosphere for 180 secs. The results of a sample A deposited underconditions without heat treatment (hereinafter, the conditions may bereferred to as “as-depo”) are also shown for reference.

As can be seen from FIG. 20, the film density of the sample A depositedunder the conditions without heat treatment was the lowest, 6.24 g/cm³,and the film densities of the sample B, the sample C, and the sample Deach subjected to the heat treatment using a furnace were as low as thatof the sample A, from 6.25 g/cm³ to 6.26 g/cm³ inclusive. The filmdensities of the sample E, the sample F, the sample G, and the sample Heach subjected to the heat treatment using an RTA apparatus were each6.28 g/cm³ or more. Thus, the CAAC-OSs that are oxides having a higherfilm density than the oxide formed without heat treatment and the oxidesformed using the heat treatment with a furnace were obtained.

As described above, an RTA step can increase the film density of anoxide semiconductor. In addition, as the temperature or time of the heattreatment employing an RTA step is increased, the film density of anoxide semiconductor can be increased to make the physical propertythereof close to that of a single-crystal oxide semiconductor.Furthermore, the heat treatment using an RTA apparatus is also effectivein improving productivity because it needs only a short time as comparedwith the case of using a common furnace.

(ESR Measurements)

A method of quantitative evaluation of excess oxygen and oxygenvacancies (V_(O)) in an oxide film by electron spin resonance (ESR)analysis is described using FIGS. 12A and 12B, FIGS. 21A to 21C, andFIG. 22.

The ESR analysis is performed by generating a magnetic field in a spacein which a specimen is placed and irradiating the specimen withmicrowaves. The magnetic flux density (H₀) and/or the microwavefrequency (v) are varied. The frequency (v) and magnetic flux density(H₀) values of the microwave absorbed by the specimen are used in theequation g=hv/μ_(B)H₀ to give the parameter g-factor. Note that h andμ_(B) represent the Planck constant and the Bohr magneton, respectively,and both are constants.

The spin density corresponding to a signal at a g-factor of 2.001 amongthe signals observed by ESR represents the number of dangling bonds. Theg-factor of the signal detected here may be greater than or equal to1.90 and less than or equal to 2.01, preferably greater than or equal to2.00 and less than or equal to 2.05.

The spin density corresponding to a signal at a g-factor of 1.93 amongsignals observed by ESR represents the number of oxygen vacancies(V_(O)). The g-factor of the signal detected here may be greater than orequal to 1.83 and less than or equal to 2.03, preferably greater than orequal to 1.90 and less than or equal to 1.95.

Here are shown the analysis results of the spin densities in an oxidesemiconductor obtained in such a manner that, after the oxidesemiconductor was formed, a silicon oxynitride film was formed over theoxide semiconductor and heat treatment was then performed.

A method of fabricating specimens is described. First, a 300-nm-thicksilicon oxynitride film was formed over a quartz substrate. For theformation of the silicon oxynitride film, silane and dinitrogen monoxidewere supplied at flow rates of 2.3 sccm and 800 sccm, respectively, assource gases into a treatment chamber, and a power of 50 W was suppliedwith the use of a 27.12 MHz high-frequency power source. The temperatureof the quartz substrate was 400° C. during the formation of the siliconoxynitride film. After the formation, heat treatment was performed at450° C. for one hour.

Next, oxygen was implanted to the silicon oxynitride film by an ionimplantation method. The conditions of the oxygen implantation were asfollows: an acceleration voltage of 60 kV and a dosage of 2×10¹⁶ions/cm².

Then, a 50-nm-thick In—Ga—Zn oxide film was formed over the siliconoxynitride film by a sputtering method. The In—Ga—Zn oxide film wasformed under the following conditions: a sputtering target having anatomic ratio of 1:1:1.2 was used; argon and oxygen were supplied at flowrates of 30 sccm and 15 sccm, respectively, as sputtering gases into adeposition chamber of a sputtering apparatus; the pressure in thedeposition chamber was controlled to be 0.4 Pa; and a DC power of 0.5 kWwas supplied. Note that the substrate temperature was 300° C. during theformation of the In—Ga—Zn oxide.

After the formation, heat treatment was performed at 450° C. in anitrogen atmosphere for one hour and then in an oxygen atmosphere forone hour.

Next, a 20-nm-thick silicon oxynitride film was formed over the In—Ga—Znoxide film. The silicon oxynitride film was formed under the followingconditions: the quartz substrate was placed in a treatment chamber of aplasma chemical vapor deposition (CVD) apparatus; silane and dinitrogenmonoxide were supplied at flow rates of 1 sccm and 800 sccm,respectively, as source gases into the treatment chamber; and a power of150 W was supplied with the use of a 60 MHz high-frequency power source.The temperature of the quartz substrate was 350° C. during the formationof the silicon oxynitride film. The pressure in the film formation was40 Pa, which might not be suitable for a gate insulating layer used in asemiconductor device of one embodiment of the present invention.

Here, the specimen that was not subjected to heat treatment was aspecimen I1. Then, the specimen that was subjected to heat treatment at350° C. in an oxygen atmosphere for one hour was a specimen 12, and aspecimen that was subjected to heat treatment at 400° C. in an oxygenatmosphere for one hour was a specimen 13.

The specimens were subjected to ESR measurements. The ESR measurementswere performed under the following conditions: the measurementtemperature was room temperature (25° C.), the high-frequency power(power of microwaves) of 9.5 GHz was 20 mW, and the direction of amagnetic field was parallel to a film surface of each specimen. Notethat the lower limit of detection of the spin density corresponding to asignal at a g-factor of 1.93 due to oxygen vacancies in the In—Ga—Znoxide was 1×10¹⁷ spins/cm³.

FIGS. 21A to 21C show the results of the ESR measurements. In the graphsshown in FIGS. 21A to 21C, the vertical axis represents a first-orderderivative of the absorption intensity of a microwave, and thehorizontal axis represents a g-factor. FIG. 21A, FIG. 21B, and FIG. 21Cshow the results of ESR measurements of the specimen I1, the specimen12, and the specimen 13, respectively. FIGS. 21A to 21C also show valuesobtained by fitting with a Gaussian profile at a g-factor of 1.93 in themeasurement results of the specimens. In each of FIGS. 21A to 21C, thedotted line indicates the measurement result and the solid lineindicates the result of the fitting. The spin density corresponding tothe absorption intensity of the microwave was obtained by calculatingthe integral value of the signal at a g-factor of around 1.93 with thefitted curve.

FIG. 22 shows the spin densities. As seen from the result of thespecimen I1, the spin density in the oxide semiconductor film was3.9×10¹⁸ spins/cm³ owing to the formation of the silicon oxynitridefilm.

However, the spin density was decreased by heat treatment performedafter the formation of the silicon oxynitride film, and became less thanthe lower limit of detection (1×10¹⁷ spins/cm³) for both the specimen 12and the specimen 13. Thus, oxygen vacancies generated in the oxidesemiconductor after formation of the silicon oxynitride film can befilled by heat treatment that is performed while the oxide semiconductoris in contact with the silicon oxynitride film.

A transistor in FIG. 12B is described as an example. When heat treatmentis performed using a film having a property of blocking oxygen as theinsulator 408, oxygen released from one or both of the insulators 402and 412 is prevented from being released to the outside of thesemiconductor 406 b of an oxide, so that more oxygen can be supplied tothe semiconductor 406 b of the oxide.

The heat treatment is preferably performed at a temperature higher thanor equal to 300° C. and lower than 450° C., further preferably higherthan or equal to 350° C. and lower than or equal to 400° C. In the casewhere a metal with a high oxygen affinity is used in the conductors 416a and 416 b in contact with a semiconductor stacked layer 406 of theoxide, the heat treatment might allow the metal to extract oxygen fromthe semiconductor stacked layer 406 of the oxide. Thus, the temperaturerange may be appropriately set so that heat treatment is performed atsuch a temperature that the amount of oxygen supplied from the insulator402 and the insulator 412 is larger than the amount of oxygen extractedto enter the conductor 416 a and the conductor 416 b.

The above heat treatment can reduce the number of oxygen vacancies inthe semiconductor 406 b of the oxide, thus stabilizing thecharacteristics of the semiconductor 406 b of the oxide. In particular,when the channel length of the transistor is shortened, the effect ofoxygen vacancies in the oxide semiconductor on the characteristics ofthe transistor becomes greater. Thus, the above heat treatment isperformed to reduce the number of oxygen vacancies in the semiconductor406 b of the oxide, so that a highly reliable semiconductor device whichcan maintain normally-off characteristics can be provided even when thechannel length is shortened.

The example of the transistor structure described above is not limitedto that in FIGS. 12A and 12B. The film having a property of blockingoxygen may be used as the insulator 418. When the film having a propertyof blocking oxygen is located above the oxide semiconductor and/or theconductor, the transistor structure may be different from that in FIGS.12A and 12B.

Furthermore, the use of ESR analysis can detect oxygen having anunpaired electron in the oxide semiconductor and a SiO_(X) film incontact with the oxide semiconductor.

Oxygen vacancies generated in an oxide semiconductor in a devicemanufacturing process might change the electrical conductivity of theoxide semiconductor. The same occurs if water or hydrogen which forms anelectron donor enters an oxide semiconductor. Such phenomena becomefactors of variation in the electric characteristics of a transistorusing the oxide semiconductor. An oxide semiconductor is preferablyformed in an oxygen-excess state so that a device can be constructedwithout generating oxygen vacancies.

Example 2

Structures of In—Sn—Zn oxides and the characteristics and reliability oftransistors including the oxides are described below.

(In—Sn—Zn Oxide Structure 1)

FIG. 40 shows X-ray diffraction (XRD) spectra of the In—Sn—Zn oxides byan out-of-plane method. A specimen T1 to a specimen T3 were eachobtained by forming an In—Sn—Zn oxide over a quartz glass substrateusing a magnetron sputtering method.

The specimen T1 was a sample obtained by forming an In—Sn—Zn oxide filmunder the following conditions: a sputtering target having an atomicratio of In:Sn:Zn=2:1:3 was used; oxygen was supplied at a flow rate of30 sccm as a sputtering gas into a deposition chamber; the pressure inthe deposition chamber was controlled to be 0.4 Pa; a DC power of 200 Wwas supplied; and the substrate temperature was 300° C. duringdeposition. The specimen T2 was a sample obtained by forming an In—Sn—Znoxide film under the following conditions: a sputtering target having anatomic ratio of In:Sn:Zn=2:1:3 was used; argon and oxygen were suppliedat flow rates of 20 sccm and 10 sccm, respectively, as sputtering gasesinto a deposition chamber; the pressure in the deposition chamber wascontrolled to be 0.4 Pa; a DC power of 200 W was supplied; and thesubstrate temperature was room temperature during deposition. Thespecimen T3 was a sample obtained by forming an In—Sn—Zn oxide filmunder the following conditions: a sputtering target having an atomicratio of In:Sn:Zn=2:1:3 was used; argon and oxygen were supplied at flowrates of 98 sccm and 2 sccm, respectively, as sputtering gases into adeposition chamber; the pressure in the deposition chamber wascontrolled to be 1.0 Pa; a DC power of 100 W was supplied; and thesubstrate temperature was room temperature during deposition.

The spectrum of the specimen T1 has a peak at a diffraction angle (2θ)of 31°. The spectra of the specimens T2 and T3 have no peak at adiffraction angle (2θ) of 31°. The peaks of the spectra of the specimensT1 to T3 at a diffraction angle (2θ) of or near 21° are due to thequartz glass substrate.

The diffraction angle (2θ) of 31°, at which the peak of the spectrum ofthe specimen T1 is located, is identical with the diffraction angle (20)at which the peak of the XRD spectrum of the CAAC-OS in FIG. 3A islocated. In other words, the spectrum of the specimen T1 in FIG. 40indicates that the In—Sn—Zn oxide film of the specimen T1 has a CAAC-OSstructure.

FIGS. 41A to 41C show TEM images of the specimens T1 to T3 observed fromthe direction substantially parallel to the specimen surface. FIG. 41A,FIG. 41B, and FIG. 41C show the cross-sectional TEM images of thespecimen T1, the specimen T2, and the specimen T3, respectively.

FIG. 41A reveals that metal atoms are arranged in a layered manner. Thelayered arrangement of metal atoms in FIG. 41A is analogous to thelayered arrangement of metal atoms of the CAAC-OS structure in FIGS. 1Aand 1B. The specimen T1 shown in FIG. 41A may have a CAAC-OS structure.

FIG. 41B shows a periodic atomic order in a microscopic region (e.g.,the region enclosed by the white frame (1) in FIG. 41B) and no crystalorientation in the whole film. FIG. 41B also shows no clear crystalgrain boundary. Features of the nc-OS described in <nc-OS> in Embodiment1 are as follows: the size of a crystal part included in a film isgreater than or equal to 1 nm and less than or equal to 3 nm; theorientation of the whole film is not observed; and a grain boundary isnot clearly observed. This indicates that the In—Sn—Zn oxide film of thespecimen T2 has an nc-OS structure.

FIG. 41C shows that the In—Sn—Zn oxide film of the specimen T3 has avoid. Since an a-like OS structure may have a void as described in<a-like OS> in Embodiment 1, the In—Sn—Zn oxide film of the specimen T3may have an a-like OS structure.

In summary, FIG. 40 and FIGS. 41A to 41C reveal that the In—Sn—Zn oxidesof the specimens T1, T2, and T3 have features of a CAAC-OS structure, annc-OS structure, and an a-like OS structure, respectively. Furthermore,since the film densities of the specimens T1, T2, and T3 are 6.3 g/cm³,6.2 g/cm³, and 5.9 g/cm³, respectively, the In—Sn—Zn oxide film of thespecimen T1 is a denser film than those of the specimens T2 and T3.

(In—Sn—Zn Oxide Structure 2)

FIGS. 42A to 42C show a crystalline structure of a specimen includingthe In—Sn—Zn oxide film that was formed under the same conditions asthose of the specimen T1 and then subjected to heat treatment at 800° C.in an atmosphere containing nitrogen at 80 vol % and oxygen at 20 vol %.FIG. 42A shows a TEM image obtained by observation from the directionsubstantially parallel to the specimen surface. FIG. 42B shows adiffraction pattern of a (100) plane obtained by nanobeam electrondiffraction (NBED) of the specimen using a nanobeam with a probediameter of 1 nm. FIG. 42C shows a diffraction pattern of a (100) planeobtained by calculation from the structure of InGaZn₂O₅ having ahomologous phase.

In FIG. 42B, the d values of spots P1, P2, and P3 are 0.285 nm, 0.172nm, and 0.281 nm, respectively. The segment between the spot P1 and thepoint O1 and the segment between the spot P2 and the point O1 form anangle (hereinafter, also referred to as ∠P1O1P2) of 36.6°. The segmentbetween the spot P2 and the point O1 and the segment between the spot P3and the point O1 form an angle (hereinafter, also referred to as∠P2O1P3) of 38.1°. The segment between the spot P3 and the point O1 andthe segment between the spot P1 and the point O1 form an angle(hereinafter, also referred to as ∠P3O1P1) of 74.4°.

In FIG. 42C, the d values of spots Q1, Q2, and Q3 are 0.282 nm, 0.177nm, and 0.276 nm, respectively. The segment between the spot Q1 and thepoint O2 and the segment between the spot Q2 and the point O2 form anangle (hereinafter, also referred to as ∠Q1O2Q2) of 38.3°. The segmentbetween the spot Q2 and the point O2 and the segment between the spot Q3and the point O2 form an angle (hereinafter, also referred to as∠Q2O2Q3) of 37.5°. The segment between the spot Q3 and the point O2 andthe segment between the spot Q1 and the point O2 form an angle(hereinafter, also referred to as ∠Q3O2Q1) of 75.8°.

FIGS. 42B and 42C show that there are substantial correspondencesbetween the d values of the spots P1 and Q1, between the d values of thespots P2 and Q2, between the d values of the spots P3 and Q3, between∠P1O1P2 and ∠Q1O2Q2, between ∠P2O1P3 and ∠Q2O2Q3, and between ∠P3O1P1and ∠Q3O2Q1. This indicates that the structure of the In—Sn—Zn oxidefilm is analogous to that of InGaZn₂O₅ having a homologous phase.

(Reliability of Transistor Including In—Sn—Zn Oxide)

Next, bias-temperature stress tests of transistors each including anIn—Sn—Zn oxide are described.

FIG. 39 is a schematic view illustrating a structure of a transistor. Atransistor 200 includes a conductor 204 (hereinafter, also referred toas a gate electrode) over a substrate 201, an insulator 212 over theconductor 204, a semiconductor 206 over the insulator 212, a conductor216 a (hereinafter, also referred to as a source electrode) and aconductor 216 b (hereinafter, also referred to as a drain electrode)which are provided with a space therebetween over the semiconductor 206,and an insulator 218 over the conductors 216 a and 216 b and thesemiconductor 206.

FIG. 43 shows the results of a test EX1 and a test EX2 on a transistorTR1 and a transistor TR2.

The test EX1 is a positive gate bias-temperature stress test in a darkenvironment, under the conditions where the temperature of a heat sourcethat applied heat to the transistor was 60° C., the potential applied tothe gate electrode was 30 V, the potential applied to the sourceelectrode was 0 V, and the potential applied to the drain electrode was0 V. The test EX2 is a negative gate bias-temperature stress test inwhich measurements were performed with the transistors irradiated withlight from a white LED, under the conditions where the temperature of aheat source that applied heat to the transistor was 60° C., thepotential applied to the gate electrode was −30 V, the potential appliedto the source electrode was 0 V, and the potential applied to the drainelectrode was 0 V. The data obtained by each of the tests EX1 and EX2are current-voltage characteristics immediately after the start of thetest (0 secs) and after the elapse of 1.0×10² secs, 6.0×10² secs,1.8×10³ secs, and 3.6×10³ secs from the start of the test. The symbolI_(D) [A] represents drain current I_(D) and the symbol VG [V]represents gate voltage V_(gs).

Structures of the transistors TR1 and TR2 are specifically described. Aschematic view of each of the transistors TR1 and TR2 are as illustratedin FIG. 39. The conductor 204 is a 150-nm-thick tungsten film formed bya sputtering method. The insulator 212 is a stack of a 400-nm-thicksilicon nitride film and a 50-nm-thick silicon oxynitride film. Theconductors 216 a and 216 b are a stacked layer of a 50-nm-thick tungstenfilm, a 400-nm-thick aluminum film, and a 100-nm-thick titanium filmformed by a sputtering method. The insulator 218 is a 450-nm-thicksilicon oxynitride film.

The semiconductor 206 of the transistor TR1 is a 20-nm-thick film of anIn—Sn—Zn oxide having a CAAC-OS structure formed under the sameconditions as those of the specimen T1. The transistor TR1 has a channellength of 6 μm and a channel width of 50 μm. The semiconductor 206 ofthe transistor TR2 is a 20-nm-thick film of an In—Sn—Zn oxide having annc-OS structure formed under the same conditions as those of thespecimen T2. The transistor TR2 has a channel length of 6 μm and achannel width of 50 μm.

The results A and B in FIG. 43 show that a positive shift in thresholdvoltage is smaller in the transistor TR1 than in the transistor TR2. Theresults C and D in FIG. 43 show that a negative shift in thresholdvoltage is smaller in the transistor TR1 than in the transistor TR2. Inother words, a transistor including the In—Sn—Zn oxide having a CAAC-OSstructure has higher reliability than a transistor including theIn—Sn—Zn oxide having an nc-OS structure.

FIG. 44 shows the results of a test EX3 of a transistor TR3.

The test EX3 is a temperature stress test in a dark environment underthe conditions where the temperature of a heat source that applied heatto the transistor was 50° C., the potential applied to the gateelectrode (hereinafter, also referred to as gate voltage) was 20 V, thepotential applied to the source electrode (hereinafter, also referred toas source voltage) was 0 V, and the potential applied to the drainelectrode (hereinafter, also referred to as drain voltage) was 20 V. Thedata obtained by the test EX3 are current-voltage characteristicsimmediately after the start of the test (0 secs) and after the elapse of1.0×10² secs, 1.0×10³ secs, 4.0×10³ secs, 8.0×10³ secs, and 1.0×10⁴ secsafter the start of the test.

A structure of the transistor TR3 is described. The transistor TR3 hasthe outline illustrated in the schematic view of FIG. 39, like thetransistors TR1 and TR2. The conductor 204 is a 150-nm-thick tungstenfilm formed by a sputtering method. The insulator 212 is a stack of a50-nm-thick silicon nitride film and a 150-nm-thick silicon oxynitridefilm. The conductors 216 a and 216 b are a stacked layer of a50-nm-thick tungsten film, a 400-nm-thick aluminum film, and a100-nm-thick titanium film formed by a sputtering method. The insulator218 is a 450-nm-thick silicon oxynitride film.

The semiconductor 206 of the transistor TR3 is a 10-nm-thick film of anIn—Sn—Zn oxide film having a CAAC-OS structure formed under the sameconditions as those of the specimen T1. The transistor TR3 has a channellength of 6 μm and a channel width of 50 μm.

FIG. 44 shows current-voltage characteristics measured from the timeimmediately after the start of the test (0 secs) to the time after theelapse of 1.0×10⁴ secs. The symbol I_(D) [A] represents drain currentI_(D) and the symbol VG [V] represents gate voltage V_(gs). The curvesof the current-voltage characteristics measured from the timeimmediately after the start of the test (0 secs) to the time after theelapse of 1.0×10⁴ secs all overlap with each other. This means that thetest EX3 does not cause a shift in the threshold voltage of thetransistor TR3. In other words, the In—Sn—Zn oxide film having a CAAC-OSstructure has high resistance to drain voltage stress. Furthermore,observation of no drain current indicates generation of no carriers ofelectrons or holes due to impact ionization.

(CPM Measurements of In—Sn—Zn Oxides)

Next, the measurement results of the density of localized states of theIn—Sn—Zn oxides by a constant photocurrent method (CPM) are described.In general, by reducing the density of localized states of a materialused as a channel formation region of a transistor, the transistor canhave stable electrical characteristics.

In order that the transistor can have a high field-effect mobility andstable electrical characteristics, the absorption coefficient due to thelocalized states obtained by the CPM measurements is preferably lowerthan 1×10⁻³ cm⁻¹, further preferably lower than 3×10⁻⁴ cm⁻¹.

The In—Sn—Zn oxides obtained by the CPM measurements are described. Thespecimen T4 of an In—Sn—Zn oxide having an nc-OS structure and thespecimen T5 of an In—Sn—Zn oxide having a CAAC-OS structure were eachobtained by the CPM measurements.

The specimen T4 was a sample obtained by forming a 100-nm-thick In—Sn—Znoxide film over a quartz substrate under the following conditions: asputtering target having an atomic ratio of In:Sn:Zn=2:1:3 was used;argon and oxygen were supplied at flow rates of 20 sccm and 10 sccm,respectively, as sputtering gases into a deposition chamber; thepressure in the deposition chamber was controlled to be 0.4 Pa; a DCpower of 200 W was supplied; and the substrate temperature was roomtemperature during deposition. The In—Sn—Zn oxide having an nc-OSstructure can be formed under these conditions as described in “In—Sn—Znoxide structure 1”.

The specimen T5 was a sample obtained by forming a 100-nm-thick In—Sn—Znoxide film over a quartz substrate under the following conditions: asputtering target having an atomic ratio of In:Sn:Zn=2:1:3 was used;oxygen was supplied at a flow rate of 30 sccm as a sputtering gas into adeposition chamber; the pressure in the deposition chamber wascontrolled to be 0.4 Pa; a DC power of 200 W was supplied; and thesubstrate temperature was 300° C. during deposition. The In—Sn—Zn oxidefilm having a CAAC-OS structure can be formed under these conditions asdescribed in “In—Sn—Zn oxide structure 1”.

To increase the accuracy of the CPM measurements, the thicknesses of themeasured In—Sn—Zn oxide films having an nc-OS structure and a CAAC-OSstructure were each 100 nm.

For the CPM measurements, a first electrode and a second electrode needto be provided in each of the In—Sn—Zn oxide film of the specimen T4 andthe In—Sn—Zn oxide film of the specimen T5. As these electrodes, a150-nm-thick tungsten film was formed by a sputtering method.

In the CPM measurements, the amount of light with which a surface of thespecimen between terminals is irradiated is adjusted so that aphotocurrent value is kept constant in the state where voltage isapplied between the first electrode and the second electrode provided incontact with the specimen T4 or the specimen T5, and then an absorptioncoefficient is derived from the amount of the irradiation light at eachwavelength. In the CPM measurements, when the specimen has a defect, theabsorption coefficient of energy which corresponds to a level at whichthe defect exists (calculated from a wavelength) is increased. Theincrease in the absorption coefficient is multiplied by a constant,whereby the defect density of the specimen can be obtained.

FIGS. 45A and 45B show the results of fitting the absorption coefficient(indicated by the dotted line) measured using a spectrophotometer, theabsorption coefficient (indicated by the solid line) obtained by the CPMmeasurements, and an extrapolated straight line (indicated by the thindotted line and also referred to as a background) corresponding to astraight portion of the absorption coefficient obtained by the CPMmeasurements. In FIGS. 45A and 45B, the energy range is higher than orequal to the energy gap of the In—Sn—Zn oxide films of the specimens T4and T5.

The straight portion in the curve indicating the absorption coefficientrepresents absorption due to the Urbach tail, and it is known that theslope of the straight portion increases due to disarrangement of atomsor lattice distortion depending on temperature in the case of amorphoussilicon or the like, for example. In FIGS. 45A and 45B, a calculatedvalue of Urbach energy is shown as an indicator of the slope of theabsorption coefficient due to the Urbach tail. Here, the Urbach energyis defined as an energy difference when the absorption coefficientchanges by one digit. As the value of Urbach energy increases, the slopeof the straight portion of the absorption coefficient is lower. Notethat the Urbach energy obtained based on the absorption coefficientobtained by the CPM measurements was 81.1 meV for the specimen T4 and86.8 meV for the specimen T5. This indicates that disarrangement ofatoms or lattice distortion depending on temperature is less likely tooccur in the In—Sn—Zn oxide having a CAAC-OS structure of the specimenT5 than in the In—Sn—Zn oxide having an nc-OS structure of the specimenT4.

As for an energy value around the center of the band gap, a portion outof the background represents absorption due to defect states in asemiconductor. As the density of defect states increases, the differencewith the background increases.

The integral value of the absorption coefficient in the energy range wasderived in such a manner that a background was subtracted from theabsorption coefficient obtained by the CPM measurements in the energyrange shown with the broken line circle in each of FIGS. 45A and 45B(see FIG. 46). As a result, the absorption coefficients due to thelocalized states of the specimen T4 and the specimen T5 were found to be4.41×10⁻² cm⁻¹ and 2.85×10⁻² cm⁻¹, respectively.

The absorption coefficients due to the localized states obtained hereare probably due to an impurity or a defect. Thus, the absorptioncoefficient due to the localized state of the specimen T5 is lower thanthe absorption coefficient due to the localized state of the specimenT4, and accordingly, the In—Sn—Zn oxide having a CAAC-OS structure wasfound to have a lower density of states due to an impurity or a defectthan the In—Sn—Zn oxide having an nc-OS structure.

A transistor including the In—Sn—Zn oxide semiconductor, which isdescribed as an example in this example, in a channel formation regioncan be used in the semiconductor device according to one embodiment ofthe present invention, so that a semiconductor device having highreliability and a property of withstanding high voltage can be provided.

The oxide semiconductor described as an example in this example is notlimited to the In—Sn—Zn oxide. For example, an In—Ga—Zn oxide may beused instead of the In—Sn—Zn oxide in some cases.

This example can be combined as appropriate with any of the otherembodiments in this specification.

Example 3

Example 2 shows the results of the test EX3 on the transistor TR3including an In—Sn—Zn oxide with a channel length of 6 μm, and the testwas the temperature stress test performed in a dark environment from 0secs to 1.0×10⁴ secs with a gate voltage of 20 V, a drain voltage of 20V, a source voltage of 0 V, and a heat source temperature of 50° C. Thisexample shows the results of temperature stress tests of transistorseach including an In—Sn—Zn oxide having a CAAC-OS structure, and thetests were performed for 1.0×10⁴ secs or more. This example also showscause analysis of the results and the results of calculations using amodel constructed for the test results.

Experiment 1

FIG. 47 shows the results of a test EX4-1 on a transistor TR4 and atransistor TR5.

The transistor TR4 is a transistor including an In—Ga—Zn oxide filmhaving a CAAC-OS structure with a channel length of 8 μm and a channelwidth of 50 μm. The transistor TR4 has a structure similar to that ofthe transistor 200 illustrated in the schematic view of FIG. 39. Thetransistor TR4 includes the conductor 204 which was a 150-nm-thicktungsten film formed by a sputtering method, the insulator 212 which wasa stacked layer of a 400-nm-thick silicon nitride film and a 50-nm-thicksilicon oxynitride film, the conductors 216 a and 216 b which werestacked layers of a 50-nm-thick tungsten film, a 400-nm-thick aluminumfilm, a 100-nm-thick titanium film formed by a sputtering method, andthe insulator 218 which was a 450-nm-thick silicon oxynitride film.

The transistor TR4 includes, as the semiconductor 206, a 35-nm-thickIn—Ga—Zn oxide film formed by a sputtering method. The In—Ga—Zn oxidefilm was formed under the following conditions: a sputtering targethaving an atomic ratio of In:Ga:Zn=1:1:1.2 was used; argon and oxygenwere supplied at flow rates of 20 sccm and 10 sccm, respectively, assputtering gases into a deposition chamber; the pressure in thedeposition chamber was controlled to be 0.4 Pa; a DC power of 200 W wassupplied; and the substrate temperature was 300° C. during deposition.

The transistor TR5 is a transistor including an In—Sn—Zn oxide filmhaving a CAAC-OS structure with a channel length of 8 μm and a channelwidth of 50 μm. The transistor TR5 has a structure similar to that ofthe transistor 200 illustrated in the schematic view of FIG. 39. Thetransistor TR5 includes the conductor 204 which was a 150-nm-thicktungsten film formed by a sputtering method, the insulator 212 which wasa stacked layer of a 400-nm-thick silicon nitride film and a 50-nm-thicksilicon oxynitride film, the conductors 216 a and 216 b which werestacked layers of a 50-nm-thick tungsten film, a 400-nm-thick aluminumfilm, a 100-nm-thick titanium film formed by a sputtering method, andthe insulator 218 which was a 450-nm-thick silicon oxynitride film.

The transistor TR5 includes, as the semiconductor 206, a 20-nm-thickIn—Sn—Zn oxide film formed by a sputtering method. The In—Sn—Zn oxidefilm was formed under the following conditions: a sputtering targethaving an atomic ratio of In:Sn:Zn=2:1:3 was used; oxygen was suppliedat a flow rate of 30 sccm as a sputtering gas into a deposition chamber;the pressure in the deposition chamber was controlled to be 0.4 Pa; a DCpower of 200 W was supplied; and the substrate temperature was 300° C.during deposition.

The test EX4-1 was a temperature stress test in a dark environment underthe conditions where the temperature of a heat source that applied heatto each of the transistors TR4 and TR5 was 50° C., the potential appliedto the gate electrode of each transistor was 20 V, the potential appliedto the drain electrode of each transistor was 20 V, and the potentialapplied to the source electrode of each transistor was 0 V. The dataobtained by the test EX4-1 are current-voltage characteristicsimmediately after the start of the test (0 secs) and after the elapse of1.0×10² secs, 3.0×10² secs, 1.0×10³ secs, 3.0×10³ secs, 6.0×10³ secs,and 1.0×10⁴ secs, 3.0×10⁴ secs, and 1.0×10⁵ secs after the start of thetest. The symbol I_(D) [A] represents drain current I_(D) and the symbolVG [V] represents gate voltage V_(gs).

When a change in gate voltage V_(gs) with a drain current I_(D) of1.0×10⁻¹² A is referred to as a shift value, the shift value of thetransistor TR4 subjected to the test EX4-1 for 1.0×10⁵ secs was +0.32 V(this shift is indicated by the arrow V_(sh) 4 in FIG. 47) and the shiftvalue of the transistor TR5 subjected to the test EX5 for 1.0×10⁵ secswas −5.32 V (this shift is indicated by the arrow V_(sh) 5 in FIG. 47).Changes in threshold voltage during the test EX4-1 performed for 1.0×10⁵secs were +1.27 V for the transistor TR4 (this shift is indicated by thearrow V_(th) 4 in FIG. 47) and +3.24 V for the transistor TR5 (thisshift is indicated by the arrow V_(th) 5 in FIG. 47). Note that there isno increase over time in the drain current I_(D) of the transistors TR4and TR5.

Particularly for the transistor TR5, the shift value was a negativevalue and the threshold voltage was moved in the positive direction,forming a hump in the current-voltage characteristics (denoted by HUMPin FIG. 47). Thus, the long-time temperature stress test on thetransistor including an In—Sn—Zn oxide in a dark environment resulted ina significant deterioration in the transport property of the transistor.

In a test EX4-2, temperature stress tests were performed on thetransistors TR4 and TR5 under the conditions where the potential appliedto the drain electrode was 20 V, the potential applied to the sourceelectrode was 0 V, the potential applied to the gate electrode was setto 0 V, 5 V, 10 V, 15 V, and 20 V, and the temperature of the heatsource was 50° C. The shift value V_(sh) of each transistor after2.4×10⁴ secs are shown in the graph.

The shift value V_(sh) of the transistor TR4 was greater than −0.2 V andless than 0.2 V for potentials from 0 V to 15 V applied to the gateelectrode, and was greater than 0.2 V for a potential of 20 V applied tothe gate electrode. The shift value V_(sh) of the transistor TR5 wasgreater than −0.2 V and less than 0.2 V, like that of the transistorTR4, for potentials from 0 V to 15 V applied to the gate electrode, andwas less than −0.6 V for a potential of 20 V applied to the gateelectrode.

The above results reveal that the shift value V_(sh) of the transistorincluding an In—Sn—Zn oxide was considerably increased by application ofa potential of 20 V to each of the drain electrode and the gateelectrode, although the shift value V_(sh) of the transistor includingan In—Ga—Zn oxide was not significantly changed.

Experiment 2

FIG. 48A shows the results of observation of hot carriers in atransistor including an In—Sn—Zn oxide. For the observation of hotcarriers, an emission microscope (PHEMOS-1000) manufactured by HamamatsuPhotonics K.K. was used and pictures were taken with a charge-coupleddevice (CCD) camera. Note that the wavelength range for observation withthe CCD camera was greater than or equal to 300 nm and less than orequal to 1100 nm (visible light region).

The transistor TR6 is a transistor including an In—Sn—Zn oxide having aCAAC-OS structure with a channel length of 10 μm and a channel width of50 μm.

The transistor TR6 has a structure similar to that of the transistor 200illustrated in the schematic view of FIG. 39. The transistor TR6includes the conductor 204 which was a 150-nm-thick tungsten film formedby a sputtering method, the insulator 212 which was a stacked layer of a400-nm-thick silicon nitride film and a 50-nm-thick silicon oxynitridefilm, the conductors 216 a and 216 b which were stacked layers of a50-nm-thick tungsten film, a 400-nm-thick aluminum film, a 100-nm-thicktitanium film formed by a sputtering method, and the insulator 218 whichwas a 450-nm-thick silicon oxynitride film.

The In—Sn—Zn oxide film was formed under the following conditions: asputtering target having an atomic ratio of In:Sn:Zn=2:1:3 was used;oxygen was supplied at a flow rate of 30 sccm as a sputtering gas into adeposition chamber; the pressure in the deposition chamber wascontrolled to be 0.4 Pa; a DC power of 200 W was supplied; and thesubstrate temperature was 300° C. during deposition.

A test EX5-1 to a test EX5-5 were performed on the transistor TR6 underthe conditions where the potential applied to the drain electrode was 20V, the potential applied to the source electrode was 0 V, and potentialsof 0 V, 5 V, 10 V, 15 V, and 20 V were applied to the gate electrode inthe respective tests. Pictures of the states of the transistor after theelapse of 1.0×10² secs from the start of the application (accumulativeobservation was performed for 60 secs in the period of 1.0×10² secs)were taken.

As illustrated in FIG. 48A, luminescence due to hot carriers was notobserved in the tests EX5-1 to EX5-5.

FIG. 48B shows the observation results of a transistor different fromthe above transistor. Pictures were taken with the same CCD camera as inthe above tests in a test EX6-1 and with an InGaAs camera in a testEX6-2. The wavelength range for observation with the InGaAs camera wasgreater than or equal to 950 nm and less than or equal to 1700 nm(infrared region). To take both of the pictures, an emission microscope(PHEMOS-1000) manufactured by Hamamatsu Photonics K.K. was used.

The transistor TR7 is a transistor including an In—Sn—Zn oxide filmhaving a CAAC-OS structure with a channel length of 50 μm and a channelwidth of 50 μm.

The transistor TR7 has a structure similar to that of the transistor 200illustrated in the schematic view of FIG. 39. The transistor TR7includes the conductor 204 which was a 150-nm-thick tungsten film formedby a sputtering method, the insulator 212 which was a stacked layer of a400-nm-thick silicon nitride film and a 50-nm-thick silicon oxynitridefilm, the conductors 216 a and 216 b which were stacked layers of a50-nm-thick tungsten film, a 400-nm-thick aluminum film, a 100-nm-thicktitanium film formed by a sputtering method, and the insulator 218 whichwas a 450-nm-thick silicon oxynitride film.

The transistor TR7 includes, as the semiconductor 206, a 20-nm-thickIn—Sn—Zn oxide film formed by a sputtering method. The In—Sn—Zn oxidefilm was formed under the following conditions: a sputtering targethaving an atomic ratio of In:Sn:Zn=2:1:3 was used; oxygen was suppliedat a flow rate of 30 sccm as a sputtering gas into a deposition chamber;the pressure in the deposition chamber was controlled to be 0.4 Pa; a DCpower of 200 W was supplied; and the substrate temperature was 300° C.during deposition.

The tests EX6-1 and EX6-2 were performed on the transistor TR7 under theconditions where the potential applied to the drain electrode was 20 V,the potential applied to the source electrode was 0 V, and the potentialapplied to the gate electrode was 20 V. Pictures of the states of thetransistor after the elapse of 1.0×10² secs from the start of theapplication (accumulative observation was performed for 60 secs in theperiod of 1.0×10² secs) were taken.

As illustrated in FIG. 48B, luminescence due to hot carriers was notobserved in the tests EX6-1 and EX6-2.

This shows that no impact ionization occurred due to hot carriers, whichis an indication that no drain avalanche hot carrier (DAHC)deterioration occurred due to impact ionization.

Experiment 3

Next, the results of the observation using scanning spreading resistancemicroscopy (SSRM) are described. In an SSRM method, a resistance valueis measured while the specimen plane is scanned with a conductive probe,and the distribution of the resistance value on the specimen plane isvisualized. In this experiment, a current measuring atomic forcemicroscope “E-sweep” manufactured by SII Nano Technology Inc. was usedfor the observation.

<Results of SSRM in the Vicinity of Drain Electrode>

FIG. 49A shows an image of a measured transistor TR8, which was takenwith an optical microscope. The transistor TR8 has a structure similarto that of the transistor 200 illustrated in the schematic view of FIG.39 and has a channel length of 8 μm and a channel width of 50 μm. Aconductor 801 a serves as one of the conductors 216 a and 216 b. Aconductor 801 b serves as the other of the conductors 216 a and 216 b. Aconductor 802 serves as the conductor 204. A semiconductor 803 serves asthe semiconductor 206. Although not shown in the figure, films servingas the insulators 212 and 218 are also included in the transistor TR8.

The transistor TR8 includes the semiconductor 803 which was a150-nm-thick tungsten film formed by a sputtering method, the insulator212 which was a stacked layer of a 400-nm-thick silicon nitride film anda 50-nm-thick silicon oxynitride film, the conductors 801 a and 801 bwhich were stacked layers of a 50-nm-thick tungsten film, a 400-nm-thickaluminum film, a 100-nm-thick titanium film formed by a sputteringmethod, and the insulator 218 which was a 450-nm-thick siliconoxynitride film.

The transistor TR8 includes, as the semiconductor 803, a 20-nm-thickIn—Sn—Zn oxide film formed by a sputtering method. The In—Sn—Zn oxidefilm was formed under the following conditions: a sputtering targethaving an atomic ratio of In:Sn:Zn=2:1:3 was used; oxygen was suppliedat a flow rate of 30 sccm as a sputtering gas into a deposition chamber;the pressure in the deposition chamber was controlled to be 0.4 Pa; a DCpower of 200 W was supplied; and the substrate temperature was 300° C.during deposition.

Photo 1 in FIG. 49B shows atomic force microscope (AFM) images of across section of the transistor TR8 along the dash-dot line U1-U2 inFIG. 49A. Note that the dash-dot line U1-U2 is along the channel widthdirection of the transistor TR8 and crosses a part of the semiconductor803 near the conductor 801 b. Photo 2 shows images of current output inthe positions shown in Photo 1 by an SSRM method. The measured crosssection was subjected to mechanical polishing with diamond abrasiveparticles and finishing polishing with colloidal silica.

The AFM images and current images in FIG. 49B are of the observedposition P4 and the observed position P5 on the dash-dot line U1-U2 ofthe transistor TR8.

AFM images and current images of a test EX7-1 and a test EX7-2 weretaken in temperature stress tests in a dark environment. In thetemperature stress tests, the temperature of a heat source that appliedheat to the transistor TR8 was 50° C., the potential applied to the gateelectrode of the transistor TR8 was 20 V, the potential applied to thedrain electrode of the transistor TR8 was 20 V, and the potentialapplied to the source electrode of the transistor TR8 was 0 V. The testEX7-1 shows AFM images and current images taken immediately after thestart of the temperature stress test, and the test EX7-2 shows AFMimages and current images taken after the elapse of 1.0×10⁵ secs.Specifically, the potentials were applied using the conductor 801 a as asource electrode, the conductor 801 b as a drain electrode, and theconductor 802 as a gate electrode.

In view of the results and grayscale bars in Photo 2 in FIG. 49B, nocurrent was observed in both the observed positions P4 and P5 in thetest EX7-1, and a current greater than or equal to 0.5 pA and less thanor equal to 3.0 pA was observed in the positions where the observedpositions P4 and P5 overlapped with the semiconductor 803 in the testEX7-2.

This means that the temperature stress tests in a dark environmentincreased the donor densities of the semiconductor 803 in the observedpositions P4 and P5 near the drain electrode.

<SSRM Results of the Middle Part of Active Layer Island>

The SSRM results of the middle part of an active layer island, which isa position out of the dash-dot line U1-U2, are next described.

FIG. 50A shows an image of a measured transistor TR9, which was takenwith an optical microscope. For the structure of the transistor TR9 andthe conductors 801 a, 801 b, and 802 and the semiconductor 803 in thetransistor TR9, the description of the transistor TR8 can be referredto.

Photo 3 in FIG. 50B shows AFM images of a cross section of thetransistor TR9 along the dash-dot line U3-U4 in FIG. 50A. Note that thedash-dot line U3-U4 is along the channel width direction of thetransistor TR9 and crosses the middle part of the semiconductor 803.Photo 4 shows images of current output in the positions shown in Photo 3by an SSRM method. Note that for the cross-section processing of thetransistor TR9, the description of the cross-section processing of thetransistor TR8 can be referred to.

The AFM images and current images in FIG. 50B are of the observedpositions P6 to P8 on the dash-dot line U3-U4 of the transistor TR9.

The AFM images and current images shown in FIG. 50B were taken after atemperature stress test was performed in a dark environment for 1.0×10⁵secs. In the temperature stress test, the temperature of a heat sourcethat applied heat to the transistor TR9 was 50° C., the potentialapplied to the gate electrode of the transistor TR9 was 20 V, thepotential applied to the drain electrode of the transistor TR9 was 20 V,and the potential applied to the source electrode of the transistor TR9was 0 V. Specifically, the potentials were applied using the conductor801 a as a source electrode, the conductor 801 b as a drain electrode,and the conductor 802 as a gate electrode.

In view of the results and grayscale bars in Photo 4 in FIG. 50B, acurrent greater than or equal to 0.5 pA and less than or equal to 3.0 pAwas observed in a part of the observed position P6. In addition, nocurrent was observed in both the observed positions P7 and P8.

This indicates that the temperature stress test in a dark environmentincreased the donor density of the observed position P6, which was anedge portion in the channel width direction of the semiconductor 803forming the active layer.

<Results of SSRM in the Vicinity of Source Electrode>

The SSRM results of vicinity of the source electrode, which is aposition out of the dash-dot line U1-U2 and the dash-dot line U3-U4, arenext described.

FIG. 51A shows an image of a measured transistor TR10, which was takenwith an optical microscope. For the structure of the transistor TR10 andthe conductors 801 a, 801 b, and 802 and the semiconductor 803 in thetransistor TR10, the description of the transistor TR8 can be referredto.

Photo 5 in FIG. 51B shows AFM images of a cross section of thetransistor TR10 along the dash-dot line U5-U6 in FIG. 51A. Note that thedash-dot line U5-U6 is along the channel width direction of thetransistor TR10 and crosses a part of the semiconductor 803 near theconductor 801 a. Photo 6 shows images of current output in the positionsshown in Photo 5 by an SSRM method. Note that for the cross-sectionprocessing of the transistor TR10, the description of the cross-sectionprocessing of the transistor TR8 can be referred to.

The AFM images and current images in FIG. 51B are of the observedpositions P9 and P10 on the dash-dot line U5-U6 of the transistor TR10.

The AFM images and current images shown in FIG. 51B were taken after atemperature stress test was performed in a dark environment for 1.0×10⁵secs. In the temperature stress test, the temperature of a heat sourcethat applied heat to the transistor TR10 was 50° C., the potentialapplied to the gate electrode of the transistor TR10 was 20 V, thepotential applied to the drain electrode of the transistor TR10 was 20V, and the potential applied to the source electrode of the transistorTR10 was 0 V. Specifically, the potentials were applied using theconductor 801 a as a source electrode, the conductor 801 b as a drainelectrode, and the conductor 802 as a gate electrode.

In view of the results and grayscale bars in Photo 6 in FIG. 51B, acurrent greater than or equal to 0.5 pA and less than or equal to 3.0 pAwas observed in a part of the observed position P9.

This indicates that the temperature stress test in a dark environmentincreased the donor density of the observed positions P9 and P10 in thesemiconductor 803 forming the active layer, near the conductor 801 a.

In summary, the above results reveal that the positions of thesemiconductor 803, which deteriorated due to the temperature stress testin a dark environment to have an increased donor density, were thevicinity of the drain electrode and the side-edge portion in the channelwidth direction.

Experiment 4

Device calculations were used to construct a model of the deteriorationwith a hump (HUMP in FIG. 47) shown in the current-voltagecharacteristics of the In—Sn—Zn oxide in Experiment 1 and the phenomenonof an increase in the donor density of the channel portion near thedrain electrode in Experiment 3, which are described below.

Using the TCAD simulator produced by Silvaco Inc., 3D calculations wereperformed.

A structure of a transistor used for the calculations is described.FIGS. 52A to 52C illustrate a structure of a transistor 700 for thecalculations. FIGS. 52A and 52C are top views of the transistor 700 andFIG. 52B is a cross-sectional view of the transistor 700 along thedash-dot line Q1-Q2. Note that in FIGS. 52A and 52C, some layers are notillustrated. In FIG. 52C, a semiconductor edge portion 704 d, asemiconductor edge portion 704 e, and ΔW are illustrated for explanationand hatching in FIG. 52A is omitted.

The transistor 700 includes a conductor 701 serving as a gate electrode,an insulator 702 over the conductor 701, and an oxide semiconductor 704over the insulator 702. The transistor 700 includes, over the insulator702 and the oxide semiconductor 704, a conductor 703 a serving as one ofa source electrode and a drain electrode and a conductor 703 b servingas the other thereof. The transistor 700 includes an insulator 705 overthe oxide semiconductor 704 and the conductors 703 a and 703 b.

The parameters and constants of the transistor 700 used in thecalculations are as follows. The conductor 701 has a thickness of 150 nmand a work function of 4.6 eV. The insulator 702 has a thickness of 550nm and a dielectric constant of 4.1. The oxide semiconductor 704 has athickness of 20 nm, an electron affinity of 4.6 eV, a 2.9 eV energybarrier between the valence and conduction bands, a dielectric constantof 15, an electron mobility of 30 cm²/Vs, and a hole mobility of 0.01cm²/Vs, and the effective densities of states in the valence andconduction bands are each 5.00×10¹⁸/cm³. An oxide semiconductor 704 b incontact with the insulator 705 has a donor density of 6.60×10⁻⁹/cm³. Anoxide semiconductor 704 a and an oxide semiconductor 704 c, which arejust under the conductor 703 a and the conductor 703 b, respectively,each have a donor density of 5.00×10¹⁸/cm³. The conductors 703 a and 703b each have a work function of 4.6 eV. The insulator 705 has adielectric constant of 4.1 and a thickness of 450 nm. The transistor 700has a channel length L of 8 μm and a channel width W of 50 μm.

In this experiment, in addition to the above parameters, the width ΔW ofeach of the semiconductor edge portions 704 d and 704 e, whichcorrespond to edge portions of the oxide semiconductor 704, and a donordensity N_(d) of each of the semiconductor edge portions 704 d and 704 ewere used as parameters. Specifically, donor densities N_(d) of1.00×10¹⁶/cm³, 5.00×10¹⁶/cm³, 1.00×10¹⁷/cm³, 5.00×10¹⁷/cm³, and1.00×10¹⁸/cm³ were used in tests EX8-1, EX8-2, EX8-3, EX8-4, and EX8-5,respectively. In each of the tests EX8-1 to EX8-5, current-voltagecharacteristics were calculated with various widths ΔW of 50 nm, 100 nm,250 nm, and 500 nm.

FIG. 53 shows the calculation results of the current-voltagecharacteristics, where dw1 represents the conditions with a width ΔW of50 nm, dw2 represents those with a width ΔW of 100 nm, dw3 representsthose with a width ΔW of 250 nm, and dw4 represents those with a widthΔW of 500 nm. The symbol I_(D) [A] represents drain current I_(D) andthe symbol VG [V] represents gate voltage V_(gs).

In the tests EX8-1 and EX8-2, the increases in width ΔW did not changethe current-voltage characteristics. In the tests EX8-3 to EX8-5, as inthe test EX4-1 on the transistor TR5 showing the current-voltagecharacteristics in FIG. 47, the increases in width ΔW resulted in thenegative shift value and the change in threshold voltage in the positivedirection, forming a hump. Thus, when the donor density N_(d) is1.00×10¹⁷/cm³ or more, the shift value is a negative value and thethreshold voltage is changed in the positive direction.

According to Experiment 1, by subjecting the transistor including anIn—Sn—Zn oxide to a long-time temperature stress test in a darkenvironment where high potentials were applied to the gate electrode andthe drain electrode, current-voltage characteristics of the transistorexhibited a negative shift value and a change in threshold voltage inthe positive direction, resulting in a deterioration of the transportproperty of the transistor. Furthermore, drain current I_(D) was notincreased in Experiment 1 and hot carriers were not observed inExperiment 2, indicating that there was no DAHC deterioration due toimpact ionization.

Furthermore, according to Experiment 3, a long-time temperature stresstest in a dark environment where high potentials were applied to thegate electrode and the drain electrode increased the donor density ofthe channel portion near the drain electrode. In Experiment 4,calculations using a deterioration model based on the results obtainedin Experiment 3 replicated the current-voltage characteristics inExperiment 1 with a negative shift value and a change in thresholdvoltage in the positive direction. Therefore, the deterioration of thetransistor due to a temperature stress test in a dark environment isattributed to the increases in the donor densities of a channel portionnear the drain electrode and a channel side-edge portion in the channelwidth direction.

Example 4

In Example 2 and Example 3, the stress tests on the transistors eachincluding an In—Sn—Zn oxide in a channel formation region and theresults are described. In this example, stress tests on transistors eachincluding an In—Ga—Zn oxide in a channel formation region and theresults are described.

Experiment 5

FIG. 54A shows the results of a test EX9-1 on a transistor TR11 and atransistor TR12, and FIG. 54B shows the results of a test EX9-2 on thetransistor TR11.

The transistors TR11 and TR12 are each a transistor including anIn—Ga—Zn oxide film having a CAAC-OS structure with a channel length of6 μm and a channel width of 50 μm. The transistor TR11 has the invertedstaggered structure illustrated in FIG. 39. The transistor TR12 has ans-channel structure based on the inverted staggered structureillustrated in FIG. 18A. Note that an active layer formed in thetransistor TR12 has not a stacked-layer structure of the insulator 606a, the semiconductor 606 b, and the insulator 606 c but a single-layerstructure (hereinafter, this single-layer semiconductor is referred toas a semiconductor 606).

The transistor TR11 includes a glass substrate as the substrate 201, theconductor 204 which was a 100-nm-thick tungsten film formed by asputtering method, the insulator 212 which was a stacked layer of a400-nm-thick silicon nitride film and a 50-nm-thick silicon oxynitridefilm, the semiconductor 206 which was a 20-nm-thick In—Ga—Zn oxide film,the conductors 216 a and 216 b which were stacked layers of a50-nm-thick tungsten film, a 400-nm-thick aluminum film, a 100-nm-thicktitanium film formed by a sputtering method, and the insulator 218 whichwas a 450-nm-thick silicon oxynitride film.

The transistor TR12 includes a glass substrate as the substrate 201, theconductor 604 which was a 100-nm-thick tungsten film formed by asputtering method, the insulator 612 which was a stacked layer of a400-nm-thick silicon nitride film and a 50-nm-thick silicon oxynitridefilm, the semiconductor 606 which was a 25-nm-thick In—Ga—Zn oxide film,the conductors 616 a and 616 b which were stacked layers of a50-nm-thick tungsten film, a 400-nm-thick aluminum film, and a100-nm-thick titanium film formed by a sputtering method, the insulator618 which was a 450-nm-thick silicon oxynitride film, and the conductor613 which was a 100-nm-thick indium tin oxide film.

The test EX9-1 was a temperature stress test in a dark environment underthe conditions where the temperature of a heat source that applied heatto each of the transistors TR11 and TR12 was 50° C., the potentialapplied to the gate electrode of each transistor was 20 V, and thepotential applied to the drain electrode of each transistor was 20 V.The data obtained by the test EX9-1 are current-voltage characteristicsimmediately after the start of the test (0 secs, denoted by “initial” inFIG. 54A) and after the elapse of 1.0×10² secs, 3.0×10² secs, 1.0×10³secs, 3.0×10³ secs, and 6.0×10³ secs after the start of the test. InFIG. 54A, the horizontal axis represents gate voltage and the verticalaxis represents drain current. In the graphs of FIG. 54A, ΔV_(th)represents a shift in threshold voltage from the start to the finish ofthe test and ΔV_(ds) represents drain-source voltage.

The test EX9-2 was a temperature stress test in a dark environment underthe conditions where the temperature of a heat source that applied heatto the transistor TR11 was 50° C., the potential applied to the gateelectrode was 30 V, and the potential applied to the drain electrode ofeach transistor was 30 V. For the data obtained by the test EX9-2 inFIG. 54B and the notes in the graph, the description of the test EX9-1in FIG. 54A can be referred to.

FIG. 54A shows that, at the finish of the stress test, the thresholdvoltage of the transistor TR11 was changed in the positive direction by0.23 V and the threshold voltage of the transistor TR12 was changed inthe negative direction by 0.26 V. The change in the threshold voltage ofthe transistor TR12 in the negative direction was attributed to anincrease in the donor density of a channel due to drain current.

For the stress applied to the transistor TR11, the amperage wasinitially 220 mA and, just before the finish of the test, 218 mA. Forthe stress applied to the transistor TR12, the amperage was initially400 mA and, just before the finish of the test, 419 mA. These revealthat the increase in the donor density of the channel of the transistorTR12 depended on the amount of current flowing in the channel.

Note that the reason for the difference in amperage between thetransistors TR11 and TR12 is that the transistor TR12 has an s-channelstructure. A transistor having an s-channel structure can have a highon-state current, as described in Embodiment 3.

The test EX9-2 was performed to observe deterioration caused by flow ofa higher current into the transistor including an In—Ga—Zn oxide than inthe test EX9-1. As shown in FIG. 54B, the test EX9-2 resulted information of a hump in the current-voltage characteristics of thetransistor TR11. In other words, the transport property of thetransistor TR11 was significantly degraded by the temperature stresstest in a dark environment where the potential applied to the gateelectrode was 30 V and the potential applied to the drain electrode was30 V.

Experiment 6

FIG. 54C shows a test EX9-3 on a transistor TR13 and a transistor TR14.

The transistors TR13 and TR14 are each a transistor including anIn—Ga—Zn oxide film having a CAAC-OS structure with a channel length of6 μm and a channel width of 10 μm. The transistor TR13 has the invertedstaggered structure illustrated in FIG. 39. The transistor TR14 has ans-channel structure based on the inverted staggered structureillustrated in FIG. 18A. Note that as in the transistor TR12, asemiconductor formed in the transistor TR14 has not a stacked-layerstructure of the insulator 606 a, the semiconductor 606 b, and theinsulator 606 c but a single-layer structure of the semiconductor 606(hereinafter, this single-layer semiconductor is referred to as asemiconductor 606).

For the materials forming the transistor TR13, the description of thetransistor TR11 can be referred to.

For the materials forming the transistor TR14, the description of thetransistor TR12 can be referred to.

The test EX9-3 was a temperature stress test in a dark environment underthe conditions where the temperature of a heat source that applied heatto each of the transistors TR13 and TR14 was 50° C., the potentialapplied to the gate electrode of each transistor was 6 V, and thepotential applied to the drain electrode of each transistor was 30 V.The data obtained by the test EX9-3 are current-voltage characteristicsimmediately after the start of the test (0 secs, denoted by “initial” inFIG. 54C) and after the elapse of 8.0×10³ secs, 1.6×10⁴ secs, and2.4×10⁴ secs after the start of the test. In FIG. 54C, the horizontalaxis represents gate voltage and the vertical axis represents draincurrent. In the graphs of FIG. 54C, ΔV_(th) represents a shift inthreshold voltage from the start to the finish of the test and ΔV_(ds)represents drain-source voltage.

FIG. 54C shows that, at the finish of the stress test, the thresholdvoltages of the transistors TR13 and TR14 were shifted in the negativedirection by 0.05 V and 0.01 V, respectively. In other words, the stresstest did not cause significant deterioration in both the transistorsTR13 and TR14.

Experiment 7

FIG. 55 shows the results of observation of hot carriers in thetransistors TR13 and TR14. For the observation of hot carriers, anemission microscope (PHEMOS-1000) manufactured by Hamamatsu PhotonicsK.K. was used and pictures were taken with a CCD camera. Note that thewavelength range for observation with the CCD camera was greater than orequal to 300 nm and less than or equal to 1100 nm (visible lightregion).

FIG. 55 shows the observation results of the transistors TR13 and TR14under the same stress conditions as those in Experiment 6 describedabove. In FIG. 55, D represents the drain electrode, G represents thegate electrode, and S represents the source electrode. From the resultsin FIG. 55, luminescence due to hot carriers, was observed from bothcorners of the drain electrode, which overlapped with the gate electrodein each of the transistors TR13 and TR14.

Experiment 6 and Experiment 7 in this example show that the transistorseach including an In—Ga—Zn oxide were highly reliable in that generationof hot carriers caused neither DAHC injection nor channel hot electron(CHE) injection.

The reason why generation of hot carriers does not cause deteriorationis that an In—Ga—Zn oxide is a wide-gap semiconductor. One cause of theDAHC injection is, for example, impact ionization in a channel. Theimpact ionization requires hot carriers to have theoretically 1.5 timesas high energy as that of the band gap of a semiconductor used as theactive layer. For an In—Ga—Zn oxide, the value of the band gap isapproximately 3 eV and therefore energy of 4.5 eV is required to causeimpact ionization. Hot carriers having such energy were not observedunder the conditions where a local electric field was applied inExperiments 5 and 6 of this example. For this reason, neither impactionization nor DAHC injection occurred in the transistors including anIn—Ga—Zn oxide under the conditions of the tests EX9-1 to EX9-3.

Example 5

Example 2 shows the results of the test EX3 on the transistor TR3including an In—Sn—Zn oxide having an nc-OS structure. The test EX3 wasthe temperature stress test performed in a dark environment for 1.0×10⁴secs with a gate voltage of 20 V, a drain voltage of 20 V, a sourcevoltage of 0 V, and a heat source temperature of 50° C. Example 3 showsthe results of the test EX4-1 on the transistor TR4 including anIn—Ga—Zn oxide having a CAAC-OS structure and the transistor TR5including an In—Sn—Zn oxide having a CAAC-OS structure. The test EX4-1was the temperature stress test performed in a dark environment for1.0×10⁵ secs with a gate voltage of 20 V, a drain voltage of 20 V, asource voltage of 0 V, and a heat source temperature of 50° C. Thisexample shows the results of temperature stress tests on transistorsincluding In—Sn—Zn oxides having a CAAC-OS structure and an nc-OSstructure, each of which were doped with oxygen in the middle of thetransistor fabrication process.

FIGS. 56A and 56B show the results of the test EX11 on the transistorTR15 and the transistor TR16, respectively. FIGS. 57A and 57B show theresults of the test EX12 on the transistor TR15 and the transistor TR16,respectively.

The transistor TR15 is a transistor including an In—Sn—Zn oxide filmhaving a CAAC-OS structure with a channel length of 6 μm and a channelwidth of 50 μm. The transistor TR15 has the same structure as atransistor 200 a illustrated in the schematic view of FIG. 58. Thetransistor 200 a includes a conductor 219 over the insulator 218, inaddition to the components of the transistor 200 illustrated in FIG. 39.The transistor TR15 includes the conductor 204 which was a 150-nm-thicktungsten film formed by a sputtering method, the insulator 212 which wasa stacked layer of a 400-nm-thick silicon nitride film and a 50-nm-thicksilicon oxynitride film, the conductors 216 a and 216 b which werestacked layers of a 50-nm-thick tungsten film, a 400-nm-thick aluminumfilm, a 100-nm-thick titanium film formed by a sputtering method, theinsulator 218 which was a 450-nm-thick silicon oxynitride film, and aninsulator 219 which was a 100-nm-thick silicon nitride film.

The transistor TR15 includes, as the semiconductor 206, a 35-nm-thickIn—Sn—Zn oxide film formed by a sputtering method. The In—Sn—Zn oxidefilm was formed under the following conditions: a sputtering targethaving an atomic ratio of In:Sn:Zn=1:1:1 was used; argon and oxygen weresupplied at flow rates of 20 sccm and 10 sccm, respectively, assputtering gases into a deposition chamber; the pressure in thedeposition chamber was controlled to be 0.4 Pa; a DC power of 200 W wassupplied; and the substrate temperature was 300° C. during deposition.

For the transistor TR15, a 5-nm-thick indium tin oxide film was formedover the insulator 218 before the insulator 219 was formed. After theindium tin oxide film was formed, heating was performed in an oxygenatmosphere to dope the indium tin oxide film with oxygen. This step cansupply oxygen to the insulator 218 and the semiconductor 206. Afterthat, the indium tin oxide film was removed by etching and the insulator219 was formed.

The transistor TR16 is a transistor including an In—Sn—Zn oxide filmhaving an nc-OS structure with a channel length of 6 μm and a channelwidth of 50 μm. The transistor TR16 has the same structure as atransistor 200 a illustrated in the schematic view of FIG. 58. Thetransistor 200 a includes a conductor 219 over the insulator 218, inaddition to the components of the transistor 200 illustrated in FIG. 39.The transistor TR16 includes the conductor 204 which was a 150-nm-thicktungsten film formed by a sputtering method, the insulator 212 which wasa stacked layer of a 400-nm-thick silicon nitride film and a 50-nm-thicksilicon oxynitride film, the conductors 216 a and 216 b which werestacked layers of a 50-nm-thick tungsten film, a 400-nm-thick aluminumfilm, a 100-nm-thick titanium film formed by a sputtering method, andthe insulator 218 which was a 450-nm-thick silicon oxynitride film.

The transistor TR16 includes, as the semiconductor 206, a 35-nm-thickIn—Sn—Zn oxide film formed by a sputtering method. The In—Sn—Zn oxidefilm was formed under the following conditions: a sputtering targethaving an atomic ratio of In:Sn:Zn=2:1:3 was used; oxygen was suppliedat a flow rate of 30 sccm as a sputtering gas into a deposition chamber;the pressure in the deposition chamber was controlled to be 0.4 Pa; a DCpower of 200 W was supplied; and the substrate temperature was 300° C.during deposition.

As in the case of the transistor TR15, for the transistor TR16, a5-nm-thick indium tin oxide film was formed over the insulator 218before the insulator 219 was formed. After the indium tin oxide film wasformed, heating was performed in an oxygen atmosphere to dope the indiumtin oxide film with oxygen. This step can supply oxygen to the insulator218 and the semiconductor 206. After that, the indium tin oxide film wasremoved by etching and the insulator 219 was formed.

FIGS. 56A and 56B show the results of the test EX11 on the transistorTR15 and the transistor TR16, respectively. The test EX11 was atemperature stress test in a dark environment where the temperature of aheat source that applied heat to each of the transistors TR15 and TR16was 60° C. and the potential applied to the gate electrode of eachtransistor 30 V. The condition 1 indicates the measurement results ofcurrent-voltage characteristics with a drain-source voltage of 0.1 V,and the condition 2 indicates the measurement results of current-voltagecharacteristics with a drain-source voltage of 20 V. The condition 2-mindicates the calculation results of the field-effect mobility based onthe data obtained in the condition 2. The data of the conditions 1, 2,and 2-m were obtained from the time T0 to the time T4. The time T0 isimmediately after the start of the test (0 secs), and the time T1, thetime T2, the time T3, and the time T4 are after the elapse of 1.0×10²secs, 6.0×10² secs, 1.8×10³ secs, and 3.6×10³ secs, respectively, fromthe start of the test. The symbol I_(D) [A] represents drain currentI_(D) and the symbol VG [V] represents gate voltage V_(gs).

FIGS. 57A and 57B show the results of the test EX12 on the transistorTR15 and the transistor TR16, respectively. The test EX12 was atemperature stress test in a dark environment where the temperature of aheat source that applied heat to each of the transistors TR15 and TR16was 60° C. and the potential applied to the gate electrode of eachtransistor was −30 V. The condition 1 indicates the measurement resultsof current-voltage characteristics with a drain-source voltage of 0.1 V,and the condition 2 indicates the measurement results of current-voltagecharacteristics with a drain-source voltage of 20 V. The condition 2-mindicates the calculation results of the field-effect mobility based onthe data obtained in the condition 2. The data of the conditions 1, 2,and 2-m were obtained from the time T0 to the time T4. The time T0 isimmediately after the start of the test (0 secs), and the time T1, thetime T2, the time T3, and the time T4 are after the elapse of 1.0×10²secs, 6.0×10² secs, 1.8×10³ secs, and 3.6×10³ secs, respectively, fromthe start of the test. The symbol I_(D) [A] represents drain currentI_(D) and the symbol VG [V] represents gate voltage V_(gs).

FIGS. 56A and 56B show that the transistors TR15 and TR16 each exhibitan extremely small shift in threshold voltage. Under the condition 2 inthe test EX11, changes in the threshold voltage of the transistor TR15and the transistor TR16 were 0.21 V in the positive direction and 0.29 Vin the positive direction, respectively. In the period from the time T0to the time T4, when a change in gate voltage V_(gs) at a drain currentI_(D) of 1.0×10⁻¹² A is referred to as a shift value, under thecondition 2 in the test EX11, the shift values of the transistor TR15and the transistor TR16 were 0.13 V and 0.27 V, respectively.

The transistors TR15 and TR16 also exhibited high field-effect mobility.The field-effect mobility was at most 27.7 cm²/(V·s) for the transistorTR15 and at most 26.1 cm²/(V·s) for the transistor TR16.

FIGS. 57A and 57B show that the transistors TR15 and TR16 each exhibitan extremely small shift in threshold voltage. Under the condition 2 inthe test EX12, changes in the threshold voltage of the transistor TR15and the transistor TR16 were 1.55 V in the negative direction and 1.23 Vin the negative direction, respectively. In the period from the time T0to the time T4, when a change in gate voltage V_(gs) at a drain currentI_(D) of 1.0×10⁻¹² A is referred to as a shift value, under thecondition 2 in the test EX12, the shift values of the transistor TR15and the transistor TR16 were −1.64 V and 1.26 V, respectively.

The transistors TR15 and TR16 also exhibited high field-effect mobility,as in the test EX11. The field-effect mobility was at most 27.4cm²/(V·s) for the transistor TR15 and at most 25.9 cm²/(V·s) for thetransistor TR16.

The above-described results of the tests EX11 and EX12 reveal thatdoping the transistor including an In—Sn—Zn oxide with oxygen enabledthe transistor to have high reliability and high field-effect mobility.

This example can be combined as appropriate with any of the otherembodiments in this specification.

This application is based on Japanese Patent Application serial no.2014-242856 filed with Japan Patent Office on Dec. 1, 2014, JapanesePatent Application serial no. 2015-047546 filed with Japan Patent Officeon Mar. 10, 2015, Japanese Patent Application serial no. 2015-118401filed with Japan Patent Office on Jun. 11, 2015, and Japanese PatentApplication serial no. 2015-126832 filed with Japan Patent Office onJun. 24, 2015, the entire contents of which are hereby incorporated byreference.

What is claimed is:
 1. A method of manufacturing an oxide by asputtering method: after supplying a sputtering gas containing at leastone of oxygen and a rare gas into a deposition chamber including atarget and a substrate, generating plasma including an ion of thesputtering gas in the vicinity of the target by generating a potentialdifference between the target and the substrate; accelerating the ion ofthe sputtering gas toward the target by the potential difference;separating a compound containing a plurality of elements, an atom of thetarget, and an aggregate of atoms of the target from the target bycollision of the accelerated ion of the sputtering gas with the target;and depositing the compound over the substrate, wherein the oxide issubjected to rapid thermal annealing at a temperature higher than atemperature at which the oxide is formed and lower than a temperature atwhich the oxide comes to have a different crystal structure, wherein theoxide has a c-axis-aligned crystalline structure, wherein a carrierdensity of the oxide is less than 8×10¹¹/cm³, and wherein a film densityof the oxide is greater than or equal to 90% of a film density obtainedwhen the oxide has a single crystal structure.
 2. The method ofmanufacturing an oxide according to claim 1, wherein the temperature ofthe rapid thermal annealing is higher than 300° C. and lower than 1500°C.
 3. The method of manufacturing an oxide according to claim 1, whereinthe rapid thermal annealing is performed in an oxygen atmosphere.
 4. Themethod of manufacturing an oxide according to claim 1, wherein a lamp isused for the rapid thermal annealing.
 5. The method of manufacturing anoxide according to claim 1, wherein the oxide is formed on a surfacehaving an amorphous structure.
 6. The method of manufacturing an oxideaccording to claim 1, wherein the target comprises indium, zinc, anelement M, and an oxygen, wherein the element M is one of aluminum,gallium, yttrium, and tin, and wherein the target comprises a regionhaving a polycrystalline structure.
 7. A semiconductor device comprisinga transistor, the transistor comprising the oxide according to claim 1.8. A method of manufacturing an oxide by a sputtering method: aftersupplying a sputtering gas containing at least one of oxygen and a raregas into a deposition chamber including a target and a substrate,generating plasma including an ion of the sputtering gas in the vicinityof the target by generating a potential difference between the targetand the substrate; accelerating the ion of the sputtering gas toward thetarget by the potential difference; separating a compound containing aplurality of elements, an atom of the target, and an aggregate of atomsof the target from the target by collision of the accelerated ion of thesputtering gas with the target; and depositing the compound over thesubstrate, wherein the oxide is subjected to rapid thermal annealing ata temperature higher than a temperature at which the oxide is formed andlower than a temperature at which the oxide comes to have a differentcrystal structure, wherein the target comprises indium, zinc, gallium,and an oxygen, wherein a carrier density of the oxide is less than8×10¹¹/cm³, and wherein a film density of the oxide is greater than orequal to 90% of a film density obtained when the oxide has a singlecrystal structure.
 9. The method of manufacturing an oxide according toclaim 8, wherein the temperature of the rapid thermal annealing ishigher than 300° C. and lower than 1500° C.
 10. The method ofmanufacturing an oxide according to claim 8, wherein the rapid thermalannealing is performed in an oxygen atmosphere.
 11. The method ofmanufacturing an oxide according to claim 8, wherein a lamp is used forthe rapid thermal annealing.
 12. The method of manufacturing an oxideaccording to claim 8, wherein the oxide is formed on a surface having anamorphous structure.
 13. The method of manufacturing an oxide accordingto claim 8, wherein the target comprises a region having apolycrystalline structure.
 14. A semiconductor device comprising atransistor, the transistor comprising the oxide according to claim 8.